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1. 发明授权

US07986008B2 SOI semiconductor components and methods for their fabrication 有权
标题翻译： SOI半导体元件及其制造方法
公开(公告)号：US07986008B2
公开(公告)日：2011-07-26
申请号：US12413185
申请日：2009-03-27
申请人： Ali Icel , Qiang Chen , Mario M. Pelella
发明人： Ali Icel , Qiang Chen , Mario M. Pelella
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823437 , H01L21/823481 , H01L21/84
摘要： SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.
摘要翻译：提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。该部件包括第一导电类型的源区和漏区以及第一半导体层中的第一掺杂浓度。在源区和漏区之间限定第二导电类型的沟道区。栅极绝缘体和栅极电极覆盖沟道区域。第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

2. 发明授权

US07531403B2 SOI semiconductor components and methods for their fabrication 有权
标题翻译： SOI半导体元件及其制造方法
公开(公告)号：US07531403B2
公开(公告)日：2009-05-12
申请号：US11538001
申请日：2006-10-02
申请人： Ali Icel , Qiang Chen , Mario M. Pelella
发明人： Ali Icel , Qiang Chen , Mario M. Pelella
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823437 , H01L21/823481 , H01L21/84
摘要： SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.
摘要翻译：提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。该部件包括第一半导体层中的第一导电类型和第一掺杂浓度的源区和漏区。在源区和漏区之间限定第二导电类型的沟道区。栅极绝缘体和栅极电极覆盖沟道区域。第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

3. 发明申请

US20080079074A1 SOI SEMICONDUCTOR COMPONENTS AND METHODS FOR THEIR FABRICATION 有权
标题翻译： SOI半导体元件及其制造方法
公开(公告)号：US20080079074A1
公开(公告)日：2008-04-03
申请号：US11538001
申请日：2006-10-02
申请人： Ali Icel , Qiang Chen , Mario M. Pelella
发明人： Ali Icel , Qiang Chen , Mario M. Pelella
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823437 , H01L21/823481 , H01L21/84
摘要： SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.
摘要翻译：提供SOI半导体元件及其制造方法，其中SOI半导体元件包括支撑半导体衬底中的MOS晶体管。根据一个实施例，该部件包括具有第一半导体层，第一半导体层上的绝缘体层和覆盖绝缘体层的第二半导体层的绝缘体上半导体衬底（SOI）衬底。该部件包括第一半导体层中的第一导电类型和第一掺杂浓度的源区和漏区。在源区和漏区之间限定第二导电类型的沟道区。栅极绝缘体和栅极电极覆盖沟道区域。第一导电类型的漂移区域位于沟道区域和漏极区域之间，漂移区域具有小于第一导电性确定掺杂剂的第一掺杂浓度的第二掺杂浓度。

4. 发明授权

US07465639B1 Method for fabricating an SOI device 有权
标题翻译： SOI器件的制造方法
公开(公告)号：US07465639B1
公开(公告)日：2008-12-16
申请号：US11133969
申请日：2005-05-20
申请人： Mario M. Pelella , Richard K. Klein , James Werking
发明人： Mario M. Pelella , Richard K. Klein , James Werking
IPC分类号： H01L21/20
CPC分类号： H01L21/84
摘要： A method is provided for fabricating a silicon on insulator (SOI) device that includes a silicon substrate, a buried insulator layer overlying the silicon substrate, and a monocrystalline silicon layer overlying the buried insulator layer. The method comprises the steps of forming an MOS capacitor coupled between a first voltage bus and a second voltage bus. The MOS capacitor has a gate electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the gate electrode material forming a second plate of the MOS capacitor. The first voltage bus is coupled to the first plate of the capacitor and the second voltage bus is coupled to the second plate of the capacitor. The method further includes forming an electrical discharge path coupling the second plate of the MOS capacitor to the silicon substrate.
摘要翻译：提供了一种用于制造绝缘体上硅（SOI）器件的方法，该器件包括硅衬底，覆盖硅衬底的掩埋绝缘体层和覆盖在掩埋绝缘体层上的单晶硅层。该方法包括以下步骤：形成耦合在第一电压总线和第二电压总线之间的MOS电容器。 MOS电容器具有形成MOS电容器的第一板的栅电极材料和形成MOS电容器的第二板的栅极电极材料下面的单晶硅层中的杂质掺杂区域。第一电压总线耦合到电容器的第一板，第二电压总线耦合到电容器的第二板。该方法还包括形成将MOS电容器的第二板耦合到硅衬底的放电路径。

5. 发明申请

US20080124884A1 METHODS FOR FABRICATING A SEMICONDUCTOR DEVICE ON AN SOI SUBSTRATE 失效
标题翻译：在SOI衬底上制造半导体器件的方法
公开(公告)号：US20080124884A1
公开(公告)日：2008-05-29
申请号：US11467634
申请日：2006-08-28
申请人： Mario M. Pelella , Darin A. Chan
发明人： Mario M. Pelella , Darin A. Chan
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823878 , H01L27/0629
摘要： Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N— and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.
摘要翻译：提供了用于在包括在衬底中形成的二极管区域的半导体层/绝缘体/衬底结构上制造SOI部件的方法。该方法包括根据一个实施例，形成穿过半导体层延伸到绝缘体的浅沟槽隔离（STI）区域。沉积覆盖STI和半导体层的多晶硅层，并且被图案化以形成至少包括第一掩模区域和第二掩模区域的多晶硅掩模。使用掩模作为蚀刻掩模，通过STI和绝缘体蚀刻第一和第二开口。 N型和P型离子通过开口注入二极管区域，形成二极管的阳极和阴极。阳极和阴极通过多晶硅掩模彼此紧密间隔并精确对准。电触点被制成阳极和阴极。

6. 发明授权

US07361534B2 Method for fabricating SOI device 失效
标题翻译：制造SOI器件的方法
公开(公告)号：US07361534B2
公开(公告)日：2008-04-22
申请号：US11127329
申请日：2005-05-11
申请人： Mario M. Pelella
发明人： Mario M. Pelella
IPC分类号： H01L21/84
CPC分类号： H01L21/823481 , H01L21/28123 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/66128 , H01L29/8611
摘要： A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer. A gate electrode material is deposited and patterned to form a gate electrode and a spacer. Impurity determining dopant ions are implanted into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.
摘要翻译：提供了一种用于制造绝缘体上半导体（SOI）器件的方法。在一个实施例中，该方法包括提供单晶硅衬底，其具有覆盖衬底的单晶硅层，并通过介电层与其分离。沉积栅极电极材料并构图以形成栅电极和间隔物。使用栅极作为离子注入掩模将杂质确定掺杂剂离子注入到单晶硅层中，以在单晶硅层中形成间隔开的源极和漏极区域，并使用间隔物作为离子注入掩模形成间隔开的单晶硅衬底，以形成间隔开的在单晶衬底中分离器件区域。然后形成接触间隔开的器件区域的电触头。

7. 发明授权

US06828607B1 Discontinuous nitride structure for non-volatile transistors 有权
标题翻译：非易失性晶体管的不连续氮化物结构
公开(公告)号：US06828607B1
公开(公告)日：2004-12-07
申请号：US10315458
申请日：2002-12-09
申请人： Mario M. Pelella , Amy C. Tu , Richard K. Klein
发明人： Mario M. Pelella , Amy C. Tu , Richard K. Klein
IPC分类号： H01L29768
CPC分类号： H01L21/76897 , H01L21/76831 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/00
摘要： A multiple independent bit Flash memory cell has a gate that includes a first oxide layer, a discontinuous nitride layer on the first oxide layer, a second oxide layer on the discontinuous nitride layer and the first oxide layer, and a polysilicon layer on the second oxide layer. The discontinuous nitride layer has regions residing at different portions of the layer. These portions are separated by the second oxide layer. Thus, with a smaller channel length, charge that otherwise would migrate from one region to the other and/or strongly influence its neighboring it is blocked/impeded by the second oxide layer. In this manner, the potential for charge sharing between the regions is reduced, and a higher density chip multiple independent bit Flash memory cells may be provided.
摘要翻译：多独立位闪存单元具有栅极，该栅极包括第一氧化物层，第一氧化物层上的不连续氮化物层，不连续氮化物层上的第二氧化物层和第一氧化物层，以及在第二氧化物层上的多晶硅层层。不连续的氮化物层具有位于该层的不同部分的区域。这些部分被第二氧化物层分离。因此，具有较小的通道长度，否则会从一个区域迁移到另一个区域的电荷和/或强烈影响其邻近的电荷被第二氧化物层阻挡/阻碍。以这种方式，减小了区域之间的电荷共享的可能性，并且可以提供更高密度的芯片多个独立的位闪存单元。

8. 发明授权

US4997775A Method for forming a complementary bipolar transistor structure including a self-aligned vertical PNP transistor 失效
标题翻译：用于形成包括自对准垂直PNP晶体管的互补双极晶体管结构的方法
公开(公告)号：US4997775A
公开(公告)日：1991-03-05
申请号：US487502
申请日：1990-02-26
申请人： Robert K. Cook , Chang-Ming Hsieh , Kiyosi Isihara , Mario M. Pelella
发明人： Robert K. Cook , Chang-Ming Hsieh , Kiyosi Isihara , Mario M. Pelella
IPC分类号： H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/73 , H01L29/732
CPC分类号： H01L21/82285 , H01L27/0826 , Y10S148/011
摘要： A method of forming a complementary bipolar transistor device includes the steps of: providing a substrate of semiconductor material including at least two electrically isolated N-type device regions having a generally planar common surface; forming a P-type buried subcollar region in a first of the device regions; forming an N-type buried subcollector region in a second of the device regions; forming an N-type base region in the common surface of the first device region; forming a layer of P-doped polysilicon over the base region in the first device region and over the second device region; patterning the layer of P-doped polysilicon to form an emitter contact generally centered on the base region of the first device region and a generally annular base contact on the second device region; forming a layer of insulating material over the patterned layer of P-doped polysilicon; forming a layer of N-doped polysilicon generally conformally over the device; patterning the layer of N-doped polysilicon to form a base contact generally surrounding the emitter contact on the first device region and an emitter contact generally surrounded by the base contact on the second device region; and heating the device at least once to drive impurities from the base and emitter contacts on the first and second device regions into the device regions whereby to form a vertical PNP transistor in the first device region and a vertical NPN transistor in the second device region.

9. 发明授权

US07465623B2 Methods for fabricating a semiconductor device on an SOI substrate 失效
标题翻译：在SOI衬底上制造半导体器件的方法
公开(公告)号：US07465623B2
公开(公告)日：2008-12-16
申请号：US11467634
申请日：2006-08-28
申请人： Mario M. Pelella , Darin A. Chan
发明人： Mario M. Pelella , Darin A. Chan
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823878 , H01L27/0629
摘要： Methods are provided for fabricating an SOI component on a semiconductor layer/insulator/substrate structure including a diode region formed in the substrate. The method comprises, in accordance with one embodiment, forming a shallow trench isolation (STI) region extending through the semiconductor layer to the insulator. A layer of polycrystalline silicon is deposited overlying the STI and the semiconductor layer and is patterned to form a polycrystalline silicon mask comprising at least a first mask region and a second mask region. First and second openings are etched through the STI and the insulator using the mask as an etch mask. N- and P-type ions are implanted into the diode region through the openings to form the anode and cathode of the diode. The anode and cathode are closely spaced and precisely aligned to each other by the polycrystalline silicon mask. Electrical contacts are made to the anode and cathode.
摘要翻译：提供了用于在包括在衬底中形成的二极管区域的半导体层/绝缘体/衬底结构上制造SOI部件的方法。根据一个实施例，该方法包括形成穿过半导体层延伸到绝缘体的浅沟槽隔离（STI）区域。沉积覆盖STI和半导体层的多晶硅层，并且被图案化以形成至少包括第一掩模区域和第二掩模区域的多晶硅掩模。使用掩模作为蚀刻掩模，通过STI和绝缘体蚀刻第一和第二开口。 N型和P型离子通过开口注入二极管区域，形成二极管的阳极和阴极。阳极和阴极通过多晶硅掩模彼此紧密间隔并精确对准。电触点被制成阳极和阴极。

10. 发明授权

US07211473B1 Method and structure for controlling floating body effects 有权
标题翻译：控制浮体效应的方法和结构
公开(公告)号：US07211473B1
公开(公告)日：2007-05-01
申请号：US10756585
申请日：2004-01-12
申请人： Mario M. Pelella , William George En , Ping-Chin Yeh
发明人： Mario M. Pelella , William George En , Ping-Chin Yeh
IPC分类号： H01L21/00
CPC分类号： H01L29/78612 , H01L29/66772
摘要： A method for forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate adjacent the gate. A facet is formed in at least one of the source/drain junctions of the integrated circuit.
摘要翻译：提供了一种用于形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。源极/漏极结形成在与栅极相邻的半导体衬底中。在集成电路的源极/漏极结中的至少一个上形成刻面。

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