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1. 发明申请

US20110153899A1 Computer Peripheral Expansion Apparatus 有权
标题翻译：计算机外设扩展装置
公开(公告)号：US20110153899A1
公开(公告)日：2011-06-23
申请号：US12644629
申请日：2009-12-22
申请人： Alfredo Aldereguia , Carl A. Morrell , Grace A. Richter
发明人： Alfredo Aldereguia , Carl A. Morrell , Grace A. Richter
IPC分类号： G06F13/20
CPC分类号： G06F13/385
摘要： Computer peripheral expansion apparatus, methods of operation, and computer program products including blade peripheral expansion units (‘BPEUs’), each BPEU including a peripheral interconnect multiplexer coupled for peripheral interconnect data communications through an upstream peripheral interconnect bus (‘PIB’) segment to a host blade, the upstream PIB segment fanned out by the multiplexer into two or more peripheral downstream interconnect channels, the multiplexer connecting the upstream PIB segment to only one of the downstream channels at a time; and the two or more downstream peripheral interconnect channels, at least one of the downstream channels connected to at least one peripheral interconnect device (‘PID’) in the BPEU, the peripheral interconnect device being a device that communicates with the host blade according to a peripheral interconnect data communications protocol, one of the downstream channels configured to connect to an upstream PIB segment in another BPEU.
摘要翻译：计算机外设扩展装置，操作方法以及计算机程序产品，包括刀片外围设备扩展单元（BPEU），每个BPEU包括一个外设互连多路复用器，用于通过上游外设互连总线（“PIB”）段到外围互连数据通信主机刀片，由多路复用器扇出的上游PIB段分成两个或更多个外围下游互连通道，多路复用器将上游PIB段一次连接到仅一条下游通道; 以及所述两个或更多个下游外围互连通道，所述下游通道中的至少一个连接到所述BPEU中的至少一个外围互连设备（“PID”），所述外围设备互连设备是根据主机刀片与所述主机刀片通信的设备外围互连数据通信协议，其中一个下游通道被配置为连接到另一个BPEU中的上游PIB段。

2. 发明授权

US08688887B2 Computer peripheral expansion apparatus 有权
标题翻译：计算机外围设备
公开(公告)号：US08688887B2
公开(公告)日：2014-04-01
申请号：US12644629
申请日：2009-12-22
申请人： Alfredo Aldereguia , Carl A Morrell , Grace A. Richter
发明人： Alfredo Aldereguia , Carl A Morrell , Grace A. Richter
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： Computer peripheral expansion apparatus, methods of operation, and computer program products including blade peripheral expansion units (‘BPEUs’), each BPEU including a peripheral interconnect multiplexer coupled for peripheral interconnect data communications through an upstream peripheral interconnect bus (‘PIB’) segment to a host blade, the upstream PIB segment fanned out by the multiplexer into two or more peripheral downstream interconnect channels, the multiplexer connecting the upstream PIB segment to only one of the downstream channels at a time; and the two or more downstream peripheral interconnect channels, at least one of the downstream channels connected to at least one peripheral interconnect device (‘PID’) in the BPEU, the peripheral interconnect device being a device that communicates with the host blade according to a peripheral interconnect data communications protocol, one of the downstream channels configured to connect to an upstream PIB segment in another BPEU.
摘要翻译：计算机外设扩展装置，操作方法以及计算机程序产品，包括刀片外围设备扩展单元（BPEU），每个BPEU包括一个外设互连多路复用器，用于通过上游外设互连总线（“PIB”）段到外围互连数据通信主机刀片，由多路复用器扇出的上游PIB段分成两个或更多个外围下游互连通道，多路复用器将上游PIB段一次连接到仅一条下游通道; 以及所述两个或更多个下游外围互连通道，所述下游通道中的至少一个连接到所述BPEU中的至少一个外围互连设备（“PID”），所述外围设备互连设备是根据主机刀片与所述主机刀片通信的设备外围互连数据通信协议，其中一个下游通道被配置为连接到另一个BPEU中的上游PIB段。

3. 发明授权

US09094162B2 Error detection and correction of a data transmission 有权
公开(公告)号：US09094162B2
公开(公告)日：2015-07-28
申请号：US13524804
申请日：2012-06-15
申请人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
发明人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
IPC分类号： H03M13/00 , H04L1/00 , H03M13/09 , H03M13/29
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/098 , H03M13/2906 , H03M13/2927 , H04L1/0061
摘要： Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.

4. 发明申请

US20130159810A1 Error Detection And Correction Of A Data Transmission 有权
公开(公告)号：US20130159810A1
公开(公告)日：2013-06-20
申请号：US13326805
申请日：2011-12-15
申请人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
发明人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/098 , H03M13/2906 , H03M13/2927 , H04L1/0061
摘要： Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.

5. 发明授权

US07485809B2 System and method for implementing a cable system 有权
标题翻译：实施电缆系统的系统和方法
公开(公告)号：US07485809B2
公开(公告)日：2009-02-03
申请号：US11100680
申请日：2005-04-06
申请人： Alfredo Aldereguia , Grace A. Richter
发明人： Alfredo Aldereguia , Grace A. Richter
IPC分类号： H01R4/00
CPC分类号： G02B6/447
摘要： A system and method for implementing a cable system is disclosed. The system includes a paddle card system that includes a card, and a circuit coupled to the card and configured to couple to a server system node. The circuit indicates when the card is properly seated when the card is plugged into the server system node. As a result, errors due to the paddle card system being improperly seated are minimized.
摘要翻译：公开了一种用于实现电缆系统的系统和方法。该系统包括一个包括卡片的卡片系统，以及耦合到该卡并被配置为耦合到服务器系统节点的电路。电路指示当卡插入服务器系统节点时卡正确就位。结果是，由于卡片卡系统被错误地安置而导致的错误被最小化。

6. 发明授权

US09054840B2 Error detection and correction of a data transmission 有权
标题翻译：错误检测和校正数据传输
公开(公告)号：US09054840B2
公开(公告)日：2015-06-09
申请号：US13326805
申请日：2011-12-15
申请人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
发明人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
IPC分类号： H03M13/00 , H04L1/00 , H03M13/09 , H03M13/29
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/098 , H03M13/2906 , H03M13/2927 , H04L1/0061
摘要： Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.
摘要翻译：数据传输的错误检测和校正包括：接收数据块，其中该块包括预定数量的字，其中每个字包括奇偶校验位，其中该数据块也是纠错码（ECC）; 根据单词的奇偶校验位来确定每个单词是否包括奇偶校验错误; 提交不包括奇偶校验错误的每个单词，如果块中只有一个单词包含奇偶校验错误：通过使用块的ECC并提交校正字来校正包含奇偶校验错误的一个单词。

7. 发明申请

US20130159809A1 Error Detection And Correction Of A Data Transmission 有权
标题翻译：数据传输的错误检测和纠正
公开(公告)号：US20130159809A1
公开(公告)日：2013-06-20
申请号：US13524804
申请日：2012-06-15
申请人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
发明人： Alfredo Aldereguia , Clifton E. Kerr , Grace A. Richter
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L1/0045 , H03M13/09 , H03M13/098 , H03M13/2906 , H03M13/2927 , H04L1/0061
摘要： Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word.
摘要翻译：数据传输的错误检测和校正包括：接收数据块，其中该块包括预定数量的字，其中每个字包括奇偶校验位，其中该数据块也是纠错码（ECC）; 根据单词的奇偶校验位来确定每个单词是否包括奇偶校验错误; 提交不包括奇偶校验错误的每个单词，如果块中仅有一个单词包含奇偶校验错误：通过使用块的ECC并提交校正字来校正包括奇偶校验错误的一个单词。

8. 发明申请

US20120204021A1 Updating Programmable Logic Devices 有权
标题翻译：更新可编程逻辑器件
公开(公告)号：US20120204021A1
公开(公告)日：2012-08-09
申请号：US13443329
申请日：2012-04-10
申请人： Alfredo Aldereguia , Grace A. Richter , William B. Schwartz
发明人： Alfredo Aldereguia , Grace A. Richter , William B. Schwartz
IPC分类号： G06F15/177
CPC分类号： G06F15/177 , G06F1/24 , G06F8/65 , G06F9/00 , G06F9/4401 , G06F9/4406 , G06F21/572
摘要： Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.
摘要翻译：在对称多处理（“SMP”）计算机中更新可编程逻辑器件（“PLD”），SMP计算机的每个计算节点包括耦合用于通过总线适配器进行数据通信的PLD，总线适配器适于通过一组一个或多个输入/输出（'I / O'）存储器地址，包括使用PLD的配置指令的更新配置主计算节点; 在引导时，PLD在SMP引导中为每个计算节点上的每个总线适配器分配独特的一组一个或多个I / O地址; 并且在SMP引导期间由主计算节点向所有计算节点提供更新，通过每个总线适配器以唯一的单独的一个或多个I / O地址集合将更新作为数据传输写入每个PLD 为每个总线适配器。

9. 发明授权

US08225081B2 Updating programmable logic devices 有权
标题翻译：更新可编程逻辑器件
公开(公告)号：US08225081B2
公开(公告)日：2012-07-17
申请号：US12486132
申请日：2009-06-17
申请人： Alfredo Aldereguia , Grace A. Richter , William B. Schwartz
发明人： Alfredo Aldereguia , Grace A. Richter , William B. Schwartz
IPC分类号： G06F15/177
CPC分类号： G06F15/177 , G06F1/24 , G06F8/65 , G06F9/00 , G06F9/4401 , G06F9/4406 , G06F21/572
摘要： Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.
摘要翻译：在对称多处理（“SMP”）计算机中更新可编程逻辑器件（“PLD”），SMP计算机的每个计算节点包括耦合用于通过总线适配器进行数据通信的PLD，总线适配器适于通过一组一个或多个输入/输出（'I / O'）存储器地址，包括使用PLD的配置指令的更新配置主计算节点; 在引导时，PLD在SMP引导中为每个计算节点上的每个总线适配器分配独特的一组一个或多个I / O地址; 并且在SMP引导期间由主计算节点向所有计算节点提供更新，通过每个总线适配器以唯一的单独的一个或多个I / O地址集合将更新作为数据传输写入每个PLD 为每个总线适配器。

10. 发明授权

US08560807B2 Accessing a logic device through a serial interface 失效
标题翻译：通过串行接口访问逻辑设备
公开(公告)号：US08560807B2
公开(公告)日：2013-10-15
申请号：US13325432
申请日：2011-12-14
申请人： Alfredo Aldereguia , James J. Parsonese , Grace A. Richter , Christopher L. Wood
发明人： Alfredo Aldereguia , James J. Parsonese , Grace A. Richter , Christopher L. Wood
IPC分类号： G06F12/00
CPC分类号： G06F12/02 , G06F2212/206 , H03K19/173
摘要： Methods, apparatuses, and computer program products for accessing a logic device through a serial interface are provided. Embodiments include receiving, by the serial interface of the logic device, a first data access request indicating a non-linear address mode, wherein the first data access request includes: a non-linear address corresponding to a non-linear index specifying a plurality of non-linear addresses, the non-linear index associating each non-linear address with one of the plurality of registers; a data count indicating an amount of data to be accessed in the first data access request; and a page offset value indicating within a register, a starting page to perform the first data access request. Embodiments also include identifying in the non-linear address mode a location within the logic device based on the non-linear address and the starting page; and performing at the identified location, by the logic device, a serial transaction in accordance with the first data access request.
摘要翻译：提供了通过串行接口访问逻辑设备的方法，设备和计算机程序产品。实施例包括通过逻辑设备的串行接口接收指示非线性地址模式的第一数据访问请求，其中第一数据访问请求包括：与非线性索引对应的非线性地址，其指定多个非线性地址，所述非线性索引将每个非线性地址与所述多个寄存器之一相关联; 指示在第一数据访问请求中要访问的数据量的数据计数; 以及指示在寄存器内的页面偏移值，用于执行第一数据访问请求的起始页。实施例还包括基于非线性地址和起始页在非线性地址模式中识别逻辑设备内的位置; 以及通过逻辑设备在所识别的位置处执行根据第一数据访问请求的串行事务。

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