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1. 发明授权

US07132342B1 Method of reducing fringing capacitance in a MOSFET 有权
标题翻译：降低MOSFET边缘电容的方法
公开(公告)号：US07132342B1
公开(公告)日：2006-11-07
申请号：US11003094
申请日：2004-12-03
申请人： Alexei Sadovnikov , Peter Johnson
发明人： Alexei Sadovnikov , Peter Johnson
IPC分类号： H01L21/336
CPC分类号： H01L29/4991 , H01L29/4983 , H01L29/6653 , H01L29/78
摘要： In a method of reducing the fringing capacitance of a MOSFET, the nitride spacers on the sides of the MOSFET gate are etched away to form trenches, which are plugged to define air spacers.
摘要翻译：在减小MOSFET的边缘电容的方法中，MOSFET栅极侧面上的氮化物间隔物被蚀刻掉以形成沟槽，其被堵塞以限定空气间隔物。

2. 发明授权

US06964907B1 Method of etching a lateral trench under an extrinsic base and improved bipolar transistor 有权
标题翻译：在外部基极和改进的双极晶体管之下蚀刻横向沟槽的方法
公开(公告)号：US06964907B1
公开(公告)日：2005-11-15
申请号：US10716276
申请日：2003-11-17
申请人： Peter J. Hopper , Alexei Sadovnikov , Vladislav Vashchenko , Peter Johnson
发明人： Peter J. Hopper , Alexei Sadovnikov , Vladislav Vashchenko , Peter Johnson
IPC分类号： H01L21/302 , H01L21/306 , H01L21/331 , H01L29/04 , H01L29/08 , H01L29/10 , H01L29/732
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/66272 , H01L29/7322
摘要： In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.
摘要翻译：在BJT中，通过在外部基极区域和集电极之间形成横向沟槽来减小外部基极到集电极电容。这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。

3. 发明申请

US20160251318A1 KYNURENINE-3-MONOOXYGENASE INHIBITORS, PHARMACEUTICAL COMPOSITIONS, AND METHODS OF USE THEREOF 有权
标题翻译：吉非烯-3-MONOOXYGENASE抑制剂，药物组合物及其使用方法
公开(公告)号：US20160251318A1
公开(公告)日：2016-09-01
申请号：US14241374
申请日：2012-08-28
申请人： Stephen Martin Courtney , Michael Prime , William Mitchell , Christopher John Brown , Paula C. De Aguiar Pena , Peter Johnson , Celia Dominguez , Leticia M. Toledo-Sherman , Ignacio Munoz
发明人： Stephen Martin Courtney , Michael Prime , William Mitchell , Christopher John Brown , Paula C. De Aguiar Pena , Peter Johnson , Celia Dominguez , Leticia M. Toledo-Sherman , Ignacio Munoz
IPC分类号： C07D239/28 , C07D403/12 , C07D405/12 , C07D405/14 , C07D401/12 , C07D405/04 , C07D491/048 , C07D491/052 , C07H13/10 , C07D413/04 , C07D471/04 , C07D409/04 , C07D417/04 , C07D403/10 , C07D405/10 , C07D401/04
CPC分类号： C07D239/28 , C07D239/42 , C07D401/04 , C07D401/12 , C07D403/04 , C07D403/10 , C07D403/12 , C07D405/04 , C07D405/10 , C07D405/12 , C07D405/14 , C07D409/04 , C07D413/04 , C07D417/04 , C07D471/04 , C07D491/048 , C07D491/052 , C07H13/10
摘要： Certain chemical entities are provided herein. Also provided are pharmaceutical compositions comprising at least one chemical entity and one or more pharmaceutically acceptable vehicle. Methods of treating patients suffering from certain diseases and disorders responsive to the inhibition of KMO activity are described, which comprise administering to such patients an amount of at least one chemical entity effective to reduce signs or symptoms of the disease or disorder are disclosed. These diseases include neurodegenerative disorders such as Huntington's disease. Also described are methods of treatment include administering at least one chemical entity as a single active agent or administering at least one chemical entity in combination with one or more other therapeutic agents. Also provided are methods for screening compounds capable of inhibiting KMO activity.
摘要翻译：本文提供了某些化学实体。还提供了包含至少一种化学物质和一种或多种药学上可接受的载体的药物组合物。描述了治疗患有对KMO活性的抑制作用的某些疾病和病症的患者的方法，其包括给予这些患者一定量的至少一种有效减少疾病或病症的体征或症状的化学实体。这些疾病包括神经变性疾病如亨廷顿氏病。还描述了治疗方法，包括给予至少一种作为单一活性剂的化学实体或与一种或多种其它治疗剂组合施用至少一种化学实体。还提供了用于筛选能够抑制KMO活性的化合物的方法。

4. 发明授权

US08674418B2 Method and apparatus for achieving galvanic isolation in package having integral isolation medium 有权
标题翻译：用于在具有整体隔离介质的包装中实现电隔离的方法和装置
公开(公告)号：US08674418B2
公开(公告)日：2014-03-18
申请号：US13214069
申请日：2011-08-19
申请人： Anindya Poddar , Vijaylaxmi Khanolkar , Ashok S. Prabhu , Peter Johnson
发明人： Anindya Poddar , Vijaylaxmi Khanolkar , Ashok S. Prabhu , Peter Johnson
IPC分类号： H01L31/062 , H01L21/70 , H01L23/552
CPC分类号： H01F17/0013 , H01F27/32 , H01F27/36 , H01F2017/008
摘要： An inductor device having an improved galvanic isolation layer arranged between a pair of coil and methods of its construction are described.
摘要翻译：描述了一种具有布置在一对线圈之间的改进的电隔离层和其构造方法的电感器件。

5. 发明授权

US08314676B1 Method of making a controlled seam laminated magnetic core for high frequency on-chip power inductors 有权
标题翻译：制造用于高频片上功率电感器的可控缝层压磁芯的方法
公开(公告)号：US08314676B1
公开(公告)日：2012-11-20
申请号：US13098656
申请日：2011-05-02
申请人： Peter Smeys , Andrei Papou , Peter Johnson , Anuraag Mohan
发明人： Peter Smeys , Andrei Papou , Peter Johnson , Anuraag Mohan
IPC分类号： H01F5/00 , H01F7/06 , H01L27/08
CPC分类号： H01F17/0033 , H01F41/046 , Y10T29/4902 , Y10T29/49075 , Y10T29/49078
摘要： A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.
摘要翻译：可用于电感器结构的受控接缝磁芯层叠体包括磁性基座和从基座基本正交地延伸的第一和第二隔开的磁性侧壁，以在其间限定接缝。受控接缝磁芯层叠可用于电感器结构，其包括：非导电下模; 形成在下模具中的多个间隔开的受控接缝下层叠片，每个磁下层层叠件具有水平底座以及从底座基本垂直向上延伸的第一和第二间隔开的侧壁，以在其间限定接缝; 形成在下模具和磁性下层叠板上的非导电隔离层; 形成在隔离层上的导电迹线; 形成在隔离层和导电迹线上的非导电上模; 以及形成在上模具中的多个间隔开的受控接缝磁性上层叠片，每个磁性上层压板具有水平底座和第一和第二隔开的侧壁，其从基座基本上垂直向上延伸以在其间限定接缝。

6. 发明申请

US20120280781A1 METHOD OF MAKING A CONTROLLED SEAM LAMINATED MAGNETIC CORE FOR HIGH FREQUENCY ON-CHIP POWER INDUCTORS 有权
标题翻译：制造用于高频片上功率电感器的受控海绵层压磁芯的方法
公开(公告)号：US20120280781A1
公开(公告)日：2012-11-08
申请号：US13098656
申请日：2011-05-02
申请人： Peter Smeys , Andrei Papou , Peter Johnson , Anuraag Mohan
发明人： Peter Smeys , Andrei Papou , Peter Johnson , Anuraag Mohan
IPC分类号： H01F27/24 , H01F41/02
CPC分类号： H01F17/0033 , H01F41/046 , Y10T29/4902 , Y10T29/49075 , Y10T29/49078
摘要： A controlled seam magnetic core lamination utilizable in an inductor structure includes a magnetic base and first and second spaced-apart magnetic sidewalls extending substantially orthogonally from the base to define a seam therebetween. The controlled seam magnetic core lamination is utilizable in an inductor structure that includes: a non-conductive lower mold; a plurality of spaced-apart controlled seam lower laminations formed in the lower mold, each magnetic lower lamination having a horizontal base and first and second spaced-apart sidewalls extending substantially vertically upward from the base to define a seam therebetween; a non-conductive isolation layer formed on the lower mold and the magnetic lower laminations; a conductive trace formed on the isolation layer; a non-conductive upper mold formed over the isolation layer and the conductive trace; and a plurality of spaced-apart controlled seam magnetic upper laminations formed in the upper mold, each magnetic upper lamination having a horizontal base and first and second spaced-apart sidewalls that extend substantially vertically upward from the base to define a seam therebetween.
摘要翻译：可用于电感器结构的受控接缝磁芯层叠体包括磁性基座和从基座基本正交地延伸的第一和第二隔开的磁性侧壁，以在其间限定接缝。受控接缝磁芯层叠可用于电感器结构，其包括：非导电下模; 形成在下模具中的多个间隔开的受控接缝下层叠片，每个磁下层片具有水平底座和第一和第二间隔开的侧壁，从侧面基本垂直向上延伸以在其间限定接缝; 形成在下模具和磁性下层叠板上的非导电隔离层; 形成在隔离层上的导电迹线; 形成在隔离层和导电迹线上的非导电上模; 以及形成在上模具中的多个间隔开的受控接缝磁性上层叠片，每个磁性上层压板具有水平底座和第一和第二隔开的侧壁，其从基座基本上垂直向上延伸以在其间限定接缝。

7. 发明授权

US08222065B1 Method and system for forming a capacitive micromachined ultrasonic transducer 有权
标题翻译：用于形成电容微加工超声换能器的方法和系统
公开(公告)号：US08222065B1
公开(公告)日：2012-07-17
申请号：US12587139
申请日：2009-10-02
申请人： Peter Smeys , Peter Johnson , Gokhan Percin
发明人： Peter Smeys , Peter Johnson , Gokhan Percin
IPC分类号： H01L29/72
CPC分类号： B06B1/0292 , H01L27/0688
摘要： A method for forming a capacitive micromachined ultrasonic transducer (CMUT) is provided that includes forming oxide features outwardly of a CMUT control chip in a silicon wafer. The oxide features are planarized. A silicon-on-insulator (SOI) wafer is bonded to the planarized oxide features. For a particular embodiment, the SOI wafer comprises a single crystal epitaxial layer, a buried oxide layer and a silicon layer, and the single crystal epitaxial layer is bonded to the planarized oxide features, after which the silicon layer and the buried oxide layer of the SOI wafer are removed, leaving the single crystal epitaxial layer bonded to the oxide layer.
摘要翻译：提供一种用于形成电容微加工超声换能器（CMUT）的方法，其包括在硅晶片中的CMUT控制芯片外部形成氧化物特征。氧化物的特征被平坦化。绝缘体上硅（SOI）晶片与平坦化的氧化物特征结合。对于特定实施例，SOI晶片包括单晶外延层，掩埋氧化物层和硅层，并且单晶外延层结合到平坦化的氧化物特征，之后硅层和掩埋氧化物层去除SOI晶片，留下单晶外延层与氧化物层结合。

8. 发明申请

US20120161294A1 Method of Batch Trimming Circuit Elements 有权
标题翻译：批量修剪电路元件的方法
公开(公告)号：US20120161294A1
公开(公告)日：2012-06-28
申请号：US12978492
申请日：2010-12-24
申请人： Peter J. Hopper , Peter Johnson , Peter Smeys , William French
发明人： Peter J. Hopper , Peter Johnson , Peter Smeys , William French
IPC分类号： H01L23/48 , H01L23/544 , H01L21/66
CPC分类号： H01L22/20 , H01L22/14 , H01L23/5228 , H01L23/5252 , H01L27/0802 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： Multiple wafers that each has multiple high-precision circuits and corresponding trim control circuits are batch trimmed in a process where each wafer is formed to include openings that expose trimmable circuit elements that are internal to the circuitry of the high-precision circuits. The high-precision circuits and trim control circuits are electrically activated during the trimming phase by metal traces that run along the saw streets. The method attaches a wafer contact structure to each wafer to electrically activate the metal traces. The method places the wafers with the wafer contact structures into a solution where the exposed trimmable circuit elements are electroplated or anodized when the actual output voltage of a high-precision circuit does not match the predicted output voltage of the high-precision circuit.
摘要翻译：在每个晶片被形成为包括暴露高精度电路的电路内部的可调节电路元件的开口的过程中，每个具有多个高精度电路和相应的微调控制电路的多个晶片被批量修整。高精度电路和微调控制电路在修整阶段通过沿着锯木街道行进的金属轨迹进行电激活。该方法将晶片接触结构连接到每个晶片以电激活金属迹线。该方法将具有晶片接触结构的晶片放置在当高精度电路的实际输出电压与高精度电路的预测输出电压不匹配时，暴露的可调节电路元件被电镀或阳极化的解决方案中。

9. 发明申请

US20110260248A1 SOI Wafer and Method of Forming the SOI Wafer with Through the Wafer Contacts and Trench Based Interconnect Structures that Electrically Connect the Through the Wafer Contacts 审中-公开
标题翻译： SOI晶片和通过晶片接触和基于沟槽的互连结构形成SOI晶片的方法，电连接结构通过晶片接点
公开(公告)号：US20110260248A1
公开(公告)日：2011-10-27
申请号：US12768295
申请日：2010-04-27
申请人： Peter Smeys , Peter Johnson , Peter J. Hopper , William French
发明人： Peter Smeys , Peter Johnson , Peter J. Hopper , William French
IPC分类号： H01L29/786 , H01L21/768
CPC分类号： H01L27/1203 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/522 , H01L2224/02372 , H01L2224/0401 , H01L2224/05 , H01L2224/13023 , H01L2224/13024 , H01L2224/131 , H01L2924/13091 , H01L2924/1461 , H01L2924/014 , H01L2924/00
摘要： A silicon-on-insulator (SOI) wafer is formed to have through-the-wafer contacts, and trench based interconnect structures on the back side of the SOI wafer that electrically connect the through-the-wafer contacts. In addition, selected ones of the through-the-wafer contacts bias the bodies of the MOS transistors.
摘要翻译：形成绝缘体上硅（SOI）晶片以具有贯穿晶片的触点，以及SOI晶片的背侧上的沟槽基互连结构，其电连接晶片间的触点。此外，通过晶片间接触的选定的一个偏压MOS晶体管的主体。

10. 发明授权

US08044755B2 MEMS power inductor 有权
标题翻译： MEMS功率电感
公开(公告)号：US08044755B2
公开(公告)日：2011-10-25
申请号：US12082209
申请日：2008-04-09
申请人： Peter Smeys , Peter Johnson
发明人： Peter Smeys , Peter Johnson
IPC分类号： H01F5/00
CPC分类号： H01F17/0006 , H01F41/046 , H01F2017/0066 , H01F2017/0086 , H01L28/10 , Y10T29/4902 , Y10T29/49073 , Y10T29/49075 , Y10T29/49124 , Y10T29/4913
摘要： A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.
摘要翻译：在半导体管芯的顶表面上形成可伸缩的MEMS电感器。 MEMS电感器包括多个磁性下层叠体，位于磁性下部叠片之上并与之隔开的圆形迹线以及位于圆形迹线之上并与圆形迹线隔开的多个上层叠体。

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