专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5886376A EEPROM having coplanar on-insulator FET and control gate 失效
标题翻译：具有共面绝缘体FET和控制栅极的EEPROM
公开(公告)号：US5886376A
公开(公告)日：1999-03-23
申请号：US673974
申请日：1996-07-01
申请人： Alexandre Acovic , Tak Hung Ning , Paul Michael Solomon
发明人： Alexandre Acovic , Tak Hung Ning , Paul Michael Solomon
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/1203 , H01L29/42324 , H01L29/7881
摘要： An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.
摘要翻译：电可擦除可编程只读存储器CEEPROM）包括场效应晶体管和在第一绝缘层上间隔开的控制栅极，形成在场效应晶体管上的第二绝缘层和控制栅极以及第二绝缘层上的公共浮栅层叠在场效应晶体管和控制栅极的沟道上，因此浮置栅极也形成场效应晶体管的栅电极。 EEPROM器件可以互连在存储器阵列中，并且多个存储器阵列可以堆叠在另一个上。本发明克服了使用非标准绝缘体上硅（SOI）CMOS工艺来制造具有高面密度的EEPROM阵列的问题。

2. 发明授权

US5960265A Method of making EEPROM having coplanar on-insulator FET and control gate 失效
标题翻译：制造具有共面绝缘体FET和控制栅极的EEPROM的方法
公开(公告)号：US5960265A
公开(公告)日：1999-09-28
申请号：US881628
申请日：1997-06-24
申请人： Alexandre Acovic , Tak Hung Ning , Paul Michael Solomon
发明人： Alexandre Acovic , Tak Hung Ning , Paul Michael Solomon
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/12 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/1203 , H01L29/42324 , H01L29/7881
摘要： An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.
摘要翻译：描述了一种EEPROM器件，其结合了场效应晶体管和在第一绝缘层上间隔开的控制栅极，在场效应晶体管上形成的第二绝缘层和控制栅极以及在第二绝缘层上的公共浮置栅极场效应晶体管和控制栅极，因此浮置栅极也形成场效应晶体管的栅电极。 EEPROM器件可以互连在存储器阵列中，并且多个存储器阵列可以堆叠在另一个上。本发明克服了使用非标准绝缘体上硅（SOI）CMOS工艺来制造具有高面密度的EEPROM阵列的问题。

3. 发明授权

US06849871B2 Fully-depleted-collector silicon-on-insulator (SOI) bipolar transistor useful alone or in SOI BiCMOS 有权
公开(公告)号：US06849871B2
公开(公告)日：2005-02-01
申请号：US09757965
申请日：2001-01-10
申请人： Tak Hung Ning
发明人： Tak Hung Ning
IPC分类号： H01L21/8249 , H01L21/331 , H01L27/12 , H01L29/08 , H01L29/73 , H01L29/40
CPC分类号： H01L29/66265 , H01L27/1203 , H01L29/0821 , H01L29/7317
摘要： A bipolar transistor structure is described incorporating an emitter, base, and collector having a fully depleted region on an insulator of a Silicon-On-Insulator (SOI) substrate without the need for a highly doped subcollector to permit the fabrication of vertical bipolar transistors on semiconductor material having a thickness of 300 nm or less and to permit the fabrication of SOI BiCMOS. The invention overcomes the problem of requiring a thick semiconductor layer in SOI to fabricate vertical bipolar transistors with low collector resistance.

4. 发明授权

US4157269A Utilizing polysilicon diffusion sources and special masking techniques 失效
标题翻译：利用多晶硅扩散源和特殊掩蔽技术
公开(公告)号：US4157269A
公开(公告)日：1979-06-05
申请号：US912919
申请日：1978-06-06
申请人： Tak Hung Ning , Hwa Nien Yu
发明人： Tak Hung Ning , Hwa Nien Yu
IPC分类号： H01L29/73 , H01L21/033 , H01L21/225 , H01L21/285 , H01L21/331
CPC分类号： H01L21/033 , H01L21/2257 , H01L21/28525 , Y10S148/051 , Y10S148/124 , Y10S148/131
摘要： A method consisting of a sequence of process steps for fabricating a bipolar transistor having base contacts formed of polysilicon material and an emitter contact formed of polysilicon material or metal. The emitter contact is self-aligned to the base contacts by the use of process steps wherein a single mask aperture is used for defining the base contacts and the emitter.
摘要翻译：一种由用于制造具有由多晶硅材料形成的基极触点和由多晶硅材料或金属形成的发射极触点的双极晶体管的一系列工艺步骤组成的方法。通过使用其中单个掩模孔用于限定基极触点和发射极的工艺步骤，发射极触点与基极触点自对准。

5. 发明申请

US20110101440A1 TWO PFET SOI MEMORY CELLS 审中-公开
标题翻译：两个PFET SOI存储器单元
公开(公告)号：US20110101440A1
公开(公告)日：2011-05-05
申请号：US12612710
申请日：2009-11-05
申请人： Jin Cai , Brian L. Ji , Tak Hung Ning
发明人： Jin Cai , Brian L. Ji , Tak Hung Ning
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823425 , H01L21/823814 , H01L21/823878 , H01L21/84 , H01L27/11521 , H01L27/11558 , H01L29/792
摘要： A CMOS device includes a silicon substrate and an electrical insulator formed over the silicon substrate. The device also includes an access pFET formed over the electrical insulator and a first gate stack and a storage pFET formed over the electrical insulator, the storage pFET including a second source region that is co-formed with the first drain region, a second channel region, and a second drain region. The device also includes a second gate stack including a second dielectric layer formed above the second channel region and a floating gate electrode formed above the second gate dielectric layer.
摘要翻译： CMOS器件包括硅衬底和形成在硅衬底上的电绝缘体。器件还包括形成在电绝缘体上的访问pFET和形成在电绝缘体上的第一栅极堆叠和存储pFET，存储pFET包括与第一漏极区域共同形成的第二源极区域，第二沟道区域，和第二漏区。该器件还包括第二栅极堆叠，其包括形成在第二沟道区上方的第二介电层和形成在第二栅极介电层上方的浮置栅电极。

6. 发明授权

US07867866B2 SOI FET with source-side body doping 有权
标题翻译：具有源极体掺杂的SOI FET
公开(公告)号：US07867866B2
公开(公告)日：2011-01-11
申请号：US12651499
申请日：2010-01-04
申请人： Jin Cai , Tak Hung Ning
发明人： Jin Cai , Tak Hung Ning
IPC分类号： H01L21/336 , H01L31/119
CPC分类号： H01L29/78612 , H01L29/66772
摘要： An SOI FET device with improved floating body is proposed. Control of the body potential is accomplished by having a body doping concentration next to the source electrode higher than the body doping concentration next to the drain electrode. The high source-side dopant concentration leads to elevated forward leakage current between the source electrode and the body, which leakage current effectively locks the body potential to the source electrode potential. Furthermore, having the source-to-body junction capacitance larger than the drain-to-body junction capacitance has additional advantages in device operation. The device has no structure fabricated for the purpose of electrically connecting the body potential to other elements of the device.
摘要翻译：提出了一种具有改进的浮体的SOI FET器件。体电位的控制是通过使源电极旁边的体掺杂浓度高于漏电极旁边的体掺杂浓度来实现的。高源侧掺杂剂浓度导致源电极和体之间的向前泄漏电流升高，这种泄漏电流有效地将体电位锁定到源极电位。此外，具有大于漏极 - 体结结电容的源极 - 体结结电容在器件操作中具有额外的优点。该装置没有制造用于将身体电势电连接到装置的其它元件的结构。

7. 发明授权

US06777809B2 BEOL decoupling capacitor 有权
标题翻译： BEOL去耦电容
公开(公告)号：US06777809B2
公开(公告)日：2004-08-17
申请号：US10323132
申请日：2002-12-19
申请人： Peter Richard Duncombe , Daniel Charles Edelstein , Robert Benjamin Laibowitz , Deborah Ann Neumayer , Tak Hung Ning , Robert Rosenberg , Thomas Mcarraoll Shaw
发明人： Peter Richard Duncombe , Daniel Charles Edelstein , Robert Benjamin Laibowitz , Deborah Ann Neumayer , Tak Hung Ning , Robert Rosenberg , Thomas Mcarraoll Shaw
IPC分类号： H01L2348
CPC分类号： H01L28/55 , H01L21/31691 , H01L23/5223 , H01L23/5329 , H01L23/642 , H01L2924/0002 , H01L2924/00
摘要： An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.
摘要翻译：本文提供介电常数为10或更大的非晶介质材料用于制造集成电路应用中的电容器。使用低于450℃的温度形成非晶介质材料; 因此，BEOL冶金不会受到不利影响。本发明的非晶质介电材料表现出良好的共形性和低的漏电流。还公开了包含本发明的电容器的镶嵌装置。

8. 发明授权

US08557693B2 Contact resistivity reduction in transistor devices by deep level impurity formation 有权
标题翻译：深层杂质形成对晶体管器件的接触电阻率降低
公开(公告)号：US08557693B2
公开(公告)日：2013-10-15
申请号：US12793046
申请日：2010-06-03
申请人： Tak Hung Ning , Zhen Zhang
发明人： Tak Hung Ning , Zhen Zhang
IPC分类号： H01L21/22
CPC分类号： H01L29/0847 , H01L21/26506 , H01L21/26513 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/456 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a low resistance contact structure in a semiconductor device includes forming a doped semiconductor region in a semiconductor substrate; forming a deep level impurity region at an upper portion of the doped semiconductor region; activating dopants in both the doped semiconductor region and the deep level impurity region by annealing; and forming a metal contact over the deep level impurity region so as to create a metal-semiconductor interface therebetween.
摘要翻译：在半导体器件中形成低电阻接触结构的方法包括在半导体衬底中形成掺杂半导体区域; 在所述掺杂半导体区域的上部形成深层杂质区域; 通过退火激活掺杂半导体区域和深层杂质区域中的掺杂剂; 以及在深层杂质区上形成金属接触，从而在它们之间产生金属 - 半导体界面。

9. 发明授权

US07170112B2 Graded-base-bandgap bipolar transistor having a constant—bandgap in the base 失效
标题翻译：在基极中具有恒定带隙的梯度基带隙双极晶体管
公开(公告)号：US07170112B2
公开(公告)日：2007-01-30
申请号：US10283705
申请日：2002-10-30
申请人： Tak Hung Ning
发明人： Tak Hung Ning
IPC分类号： H01L29/739 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/66318 , H01L29/7371 , H01L29/7378
摘要： A bipolar transistor structure and process technology is described incorporating a emitter, a base, and a collector, with most of the intrinsic base adjacent the collector having a graded energy bandgap and a layer of the intrinsic base adjacent the emitter having a substantially constant energy bandgap. The invention has a smaller base transit time than a conventional graded-base-bandgap bipolar transistor.
摘要翻译：描述了双极晶体管结构和工艺技术，其结合了发射极，基极和集电极，其中与集电极相邻的大部分本征基极具有梯度能带隙和邻近发射极的本征基极层具有基本恒定的能带隙。本发明具有比传统的梯度基带隙双极晶体管更小的基极传输时间。

10. 发明授权

US5723370A FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures 失效
公开(公告)号：US5723370A
公开(公告)日：1998-03-03
申请号：US713061
申请日：1996-09-12
申请人： Tak Hung Ning , Ben Song Wu
发明人： Tak Hung Ning , Ben Song Wu
IPC分类号： H01L21/331 , H01L21/336 , H01L27/12 , H01L29/786 , H01L21/84
CPC分类号： H01L29/66265 , H01L27/1203 , H01L29/66666 , H01L29/78642
摘要： A process for fabricating Ultra Large Scale Integrated (ULSI) circuits in Silicon On Insulator (SOI) technology in which the device structures, which can be bipolar, FET, or a combination, are formed in vertical silicon sidewalls having insulation under and in back thereof so as to create SKI device structures. The silicon sidewall device SOI structures, when fabricated, take the form of cells with each cell having a plurality of either bipolar devices, FET devices, or a combination of these devices, such as collectors, emitters, bases, sources, drains, and gates interconnected within the planes of the regions of the devices in the cells and can be interconnected within the planes of the regions of devices in adjacent cells. Further, the interconnections to adjacent cells can be made from the back of the silicon sidewalls.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式