专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06209073B1 System and method for interlocking barrier operations in load and store queues 失效
标题翻译：在负载和存储队列中互锁屏障操作的系统和方法
公开(公告)号：US06209073B1
公开(公告)日：2001-03-27
申请号：US09066961
申请日：1998-04-27
申请人： Alexander Edward Okpisz , Thomas Albert Petersen , Amy May Tuvell , Ronny Lee Arnold
发明人： Alexander Edward Okpisz , Thomas Albert Petersen , Amy May Tuvell , Ronny Lee Arnold
IPC分类号： G06F1208
CPC分类号： G06F9/30043 , G06F9/3004 , G06F9/30087 , G06F9/3834
摘要： Storage access blocking instructions, such as the EIEIO instruction implemented within the PowerPC architecture, block other storage access instructions at the bus interface stage as opposed to the execute stage. Therefore, cacheable instructions, and other similar instructions, are allowed to complete without being blocked by such an EIEIO instruction not ordered by the EIEIO instruction.
摘要翻译：存储访问阻塞指令，例如在PowerPC架构中实现的EIEIO指令，阻止总线接口阶段的其他存储访问指令，而不是执行阶段。因此，可缓存指令和其他类似的指令被允许完成，而不被EIEIO指令未排序的EIEIO指令所阻止。

2. 发明授权

US06651164B1 System and method for detecting an erroneous data hazard between instructions of an instruction group and resulting from a compiler grouping error 有权
标题翻译：用于检测指令组的指令之间的错误数据危险并由编译器分组错误导致的系统和方法
公开(公告)号：US06651164B1
公开(公告)日：2003-11-18
申请号：US09418286
申请日：1999-10-14
申请人： Donald Charles Soltis, Jr. , Ronny Lee Arnold
发明人： Donald Charles Soltis, Jr. , Ronny Lee Arnold
IPC分类号： G06F1500
CPC分类号： G06F9/3853 , G06F9/3838
摘要： A superscalar processing system that detects data hazards within instruction groups transmitted to the processing system utilizes a content-addressable memory, a plurality of pipelines, an instruction dispersal unit (IDU), and a control mechanism. The IDU receives an instruction group that includes a plurality of instructions and transmits the instructions of the instruction group to the plurality of pipelines. The control mechanism stores register identifiers of the instructions in the content-addressable memory and determines whether a register identifier of one of the instructions is stored in the content-addressable memory. When the register identifier of the one instruction is stored in the content-addressable memory, the control mechanism transmits a warning signal indicating that one of the instruction groups contained a data hazard.
摘要翻译：检测发送到处理系统的指令组内的数据危害的超标量处理系统利用内容可寻址存储器，多个管线，指令分散单元（IDU）和控制机构。 IDU接收包括多个指令的指令组，并将指令组的指令发送到多个管线。所述控制机构将所述指令的寄存器标识符存储在所述内容寻址存储器中，并且确定所述指令之一的寄存器标识符是否存储在所述内容寻址存储器中。当一个指令的寄存器标识符存储在内容可寻址存储器中时，控制机构发送指示一个指令组包含数据危险的警告信号。

3. 发明授权

US07213132B2 System and method for providing predicate data to multiple pipeline stages 有权
标题翻译：用于向多个流水线阶段提供谓词数据的系统和方法
公开(公告)号：US07213132B2
公开(公告)日：2007-05-01
申请号：US10648960
申请日：2003-08-27
申请人： Gary J Benjamin , Donald Charles Soltis, Jr. , Ronny Lee Arnold
发明人： Gary J Benjamin , Donald Charles Soltis, Jr. , Ronny Lee Arnold
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/30072
摘要： A processing system provides predicate data that indicates whether instructions processed by a processor pipeline should be executed by the pipeline. In architecture, the system of the present invention utilizes a register, a pipeline, and predicate circuitry. The pipeline includes a first stage and a second stage for processing instructions of a computer program. The predicate circuitry is configured to read a first predicate value from the register and to receive a second predicate value. The predicate circuitry may transmit the first predicate value read from the register to the first stage and then select between the first predicate value and the second predicate value. The predicate value selected by the predicate circuitry is transmitted to the second stage.
摘要翻译：处理系统提供指示由处理器流水线处理的指令是否应由流水线执行的谓词数据。在架构中，本发明的系统利用寄存器，流水线和谓词电路。流水线包括用于处理计算机程序的指令的第一阶段和第二阶段。谓词电路被配置为从寄存器读取第一谓词值并接收第二谓词值。谓词电路可以将从寄存器读取的第一谓词值传送到第一级，然后在第一谓词值和第二谓词值之间进行选择。由谓词电路选择的谓词值被传送到第二阶段。

4. 发明授权

US06643762B1 Processing system and method utilizing a scoreboard to detect data hazards between instructions of computer programs 有权
标题翻译：使用记分板来检测计算机程序指令之间的数据危害的处理系统和方法
公开(公告)号：US06643762B1
公开(公告)日：2003-11-04
申请号：US09490392
申请日：2000-01-24
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F1576
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Generally, the present invention provides a processing system and method for indicating when there is a pending write to a general register of the processing system. The processing system of the present invention utilizes a plurality of general registers, a plurality of connections, a pipeline, a scoreboard, and hazard detection circuitry. The plurality of connections corresponds respectively with the general registers. The scoreboard maintains a plurality of bits such that each bit indicates whether there is a pending write to a corresponding general register. The scoreboard transmits to the hazard detection circuitry one of the bits that is indicative of whether a pending write to the one general register exists based on a value of the one bit and based on which of the connections is used to transmit the one bit. The hazard detection circuitry then detects whether a data hazard exists based on the one bit.
摘要翻译：通常，本发明提供一种处理系统和方法，用于指示什么时候有待处理系统的通用寄存器的写入。本发明的处理系统利用多个通用寄存器，多个连接，流水线，记分板和危险检测电路。多个连接分别对应于通用寄存器。记分板维持多个位，使得每个位指示是否存在对相应的通用寄存器的未决写入。记分板将危险检测电路中的一个位发送到指示基于一位的值并基于哪个连接用于发送一位的一个通用寄存器的挂起写入。危险检测电路然后根据该位检测是否存在数据危害。

5. 发明授权

US06618802B1 Superscalar processing system and method for selectively stalling instructions within an issue group 有权
标题翻译：超标量处理系统和方法，用于选择性地停止问题组内的指令
公开(公告)号：US06618802B1
公开(公告)日：2003-09-09
申请号：US09390199
申请日：1999-09-07
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F938
CPC分类号： G06F9/3855 , G06F9/3838 , G06F9/3853 , G06F9/3867
摘要： A processing system receives instructions from a computer program. Each instruction is included within an issue group such that each issue group only includes instructions that may be simultaneously processed. The issue groups are then sequentially transmitted to a plurality of pipelines that simultaneously processes and executes the instructions within the issue groups in program order. During execution, the instructions within an issue group are analyzed to determine whether any of the instructions in the issue group is dependent on unavailable data. Any of the instructions in the issue group determined to be dependent on unavailable data are independently stalled, while execution of other instructions in the issue group is allowed to continue.
摘要翻译：处理系统从计算机程序接收指令。每个指令都包含在一个问题组中，使得每个问题组只包括可以同时处理的指令。然后将问题组顺序地发送到多个管道，其同时以程序顺序处理和执行问题组内的指令。在执行期间，分析问题组中的指令以确定问题组中的任何指令是否依赖于不可用数据。确定依赖于不可用数据的问题组中的任何指令都被独立停止，同时可以继续执行问题组中的其他指令。

6. 发明授权

US07146490B2 Processing system and method for efficiently enabling detection of data hazards for long latency instructions 失效
标题翻译：处理系统和方法，用于有效地实现对长时间延迟指令的数据危害的检测
公开(公告)号：US07146490B2
公开(公告)日：2006-12-05
申请号：US10636073
申请日：2003-08-07
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Generally, the present invention provides a processing system and method for indicating when there is a pending write to a general register of the processing system. The processing system of the present invention utilizes a plurality of general registers, a plurality of connections, a pipeline, a scoreboard, and hazard detection circuitry. The plurality of connections corresponds respectively with the general registers. The scoreboard maintains a plurality of bits such that each bit indicates whether there is a pending write to a corresponding general register. The scoreboard transmits to the hazard detection circuitry one of the bits that is indicative of whether a pending write to the one general register exists based on a value of the one bit and based on which of the connections is used to transmit the one bit. The hazard detection circuitry then detects whether a data hazard exists based on the one bit.
摘要翻译：通常，本发明提供一种处理系统和方法，用于指示什么时候有待处理系统的通用寄存器的写入。本发明的处理系统利用多个通用寄存器，多个连接，流水线，记分板和危险检测电路。多个连接分别对应于通用寄存器。记分板维持多个位，使得每个位指示是否存在对相应的通用寄存器的未决写入。记分板将危险检测电路中的一个位发送到指示基于一位的值并基于哪个连接用于发送一位的一个通用寄存器的挂起写入。危险检测电路然后根据该位检测是否存在数据危害。

7. 发明授权

US06715060B1 Utilizing a scoreboard with multi-bit registers to indicate a progression status of an instruction that retrieves data 失效
标题翻译：利用具有多位寄存器的记分板来指示检索数据的指令的进度状态
公开(公告)号：US06715060B1
公开(公告)日：2004-03-30
申请号：US09493986
申请日：2000-01-28
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F940
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/3857
摘要： Generally, the present invention provides a system and method for processing instructions of a computer program and for indicating instruction attribute and/or status information so that the efficiency of the processing system may be increased. In architecture, the system of the present invention utilizes a pipeline, a scoreboard, and hazard detection circuitry. The pipeline processes and executes instructions of a computer program. Many of the instructions include register identifiers that identify registers where data should be written when the instructions are executed. When the data produced by execution of one of the instructions has yet to be written to the register identified by the one instruction's register identifier and is unavailable for use in executing other instructions of the program, the one instruction's register identifier is transmitted to the scoreboard. The scoreboard includes a plurality of multi-bit registers, and a first bit in one of the multi-bit registers is changed based on the received register identifier. The scoreboard also may receive data associated with the one instruction and may change a second bit in the one register based on the received data. Therefore, each register in the scoreboard indicates whether a pending write to a particular register exists and indicates information associated with the instruction causing the pending write.
摘要翻译：通常，本发明提供一种用于处理计算机程序的指令并用于指示指令属性和/或状态信息的系统和方法，使得可以增加处理系统的效率。在架构中，本发明的系统利用流水线，记分板和危险检测电路。流水线处理并执行计算机程序的指令。许多指令包括寄存器标识符，用于标识执行指令时应写入数据的寄存器。当执行指令之一产生的数据尚未写入由一个指令的寄存器标识符识别的寄存器，并且不能用于执行程序的其他指令时，一个指令的寄存器标识符被传送到记分板。记分板包括多个多位寄存器，并且多位寄存器之一中的第一位基于所接收的寄存器标识来改变。记分板还可以接收与该指令相关联的数据，并且可以基于所接收的数据改变该一个寄存器中的第二位。因此，记分板中的每个寄存器指示是否存在对特定寄存器的挂起写入，并且指示与引起挂起写入的指令相关联的信息。

8. 发明授权

US06622238B1 System and method for providing predicate data 有权
标题翻译：用于提供谓词数据的系统和方法
公开(公告)号：US06622238B1
公开(公告)日：2003-09-16
申请号：US09490395
申请日：2000-01-24
申请人： Gary J Benjamin , Donald Charles Soltis, Jr. , Ronny Lee Arnold
发明人： Gary J Benjamin , Donald Charles Soltis, Jr. , Ronny Lee Arnold
IPC分类号： G06F930
CPC分类号： G06F9/3867 , G06F9/30072
摘要： A processing system provides predicate data that indicates whether instructions processed by a processor pipeline should be executed by the pipeline. In architecture, the system of the present invention utilizes a register, a pipeline, and predicate circuitry. The pipeline includes a first stage and a second stage for processing instructions of a computer program. The predicate circuitry is configured to read a first predicate value from the register and to receive a second predicate value. The predicate circuitry may transmit the first predicate value read from the register to the first stage and then select between the first predicate value and the second predicate value. The predicate value selected by the predicate circuitry is transmitted to the second stage.
摘要翻译：处理系统提供指示由处理器管线处理的指令是否应由流水线执行的谓词数据。在架构中，本发明的系统利用寄存器，流水线和谓词电路。流水线包括用于处理计算机程序的指令的第一阶段和第二阶段。谓词电路被配置为从寄存器读取第一谓词值并接收第二谓词值。谓词电路可以将从寄存器读取的第一谓词值传送到第一级，然后在第一谓词值和第二谓词值之间进行选择。由谓词电路选择的谓词值被传送到第二阶段。

9. 发明授权

US06490674B1 System and method for coalescing data utilized to detect data hazards 失效
标题翻译：用于检测数据危害的数据的系统和方法
公开(公告)号：US06490674B1
公开(公告)日：2002-12-03
申请号：US09493504
申请日：2000-01-28
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F938
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3867
摘要： The present invention generally relates to a processing system and method for coalescing instruction data to efficiently detect data hazards between instructions of a computer program. In architecture, the system of the present invention utilizes a plurality of pipelines, coalescing circuitry, and hazard detection circuitry. Each of the pipelines receives and processes instructions of a computer program, and the coalescing circuitry receives a plurality of register identifiers from the pipelines. Each of the register identifiers identifies one of a plurality of registers, and the coalescing circuitry combines the plurality of register identifiers into a single register identifier such that the single register identifier identifies each of the registers identified by the register identifiers received by the coalescing circuitry. The hazard detection circuitry then compares the single register identifier with other information received by the hazard detection circuitry to detect whether a particular type of data hazard exists. Due to the combining steps of the coalescing circuitry, the number of compares by the hazard detection circuitry required to detect data hazards can be reduced, and the circuitry and complexity of implementing the hazard detection circuitry can be reduced, as well.
摘要翻译：本发明一般涉及一种用于聚合指令数据以有效地检测计算机程序的指令之间的数据危害的处理系统和方法。在架构中，本发明的系统利用多个管道，聚结电路和危害检测电路。每个管道接收和处理计算机程序的指令，并且聚结电路从管道接收多个寄存器标识符。每个寄存器标识符识别多个寄存器中的一个，并且聚结电路将多个寄存器标识符组合成单个寄存器标识符，使得单个寄存器标识符标识由由聚结电路接收的寄存器标识符识别的每个寄存器。危险检测电路然后将单个寄存器标识符与由危险检测电路接收的其它信息进行比较，以检测是否存在特定类型的数据危害。由于聚结电路的组合步骤，可以减少检测数据危害所需的危害检测电路的比较数量，并且还可以减少实施危险检测电路的电路和复杂性。

10. 发明授权

US07243215B2 System and method for utilizing a scoreboard to indicate information pertaining to pending register writes 失效
标题翻译：用于利用记分板来指示关于挂起的注册写入的信息的系统和方法
公开(公告)号：US07243215B2
公开(公告)日：2007-07-10
申请号：US10648966
申请日：2003-08-27
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/3857
摘要： Generally, the present invention provides a system and method for processing instructions of a computer program and for indicating instruction attribute and/or status information so that the efficiency of the processing system may be increased. In architecture, the system of the present invention utilizes a pipeline, a scoreboard, and hazard detection circuitry. The pipeline processes and executes instructions of a computer program. Many of the instructions include register identifiers that identify registers where data should be written when the instructions are executed. When the data produced by execution of one of the instructions has yet to be written to the register identified by the one instruction's register identifier and is unavailable for use in executing other instructions of the program, the one instruction's register identifier is transmitted to the scoreboard. The scoreboard includes a plurality of multi-bit registers, and a first bit in one of the multi-bit registers is changed based on the received register identifier. The scoreboard also may receive data associated with the one instruction and may change a second bit in the one register based on the received data. Therefore, each register in the scoreboard indicates whether a pending write to a particular register exists and indicates information associated with the instruction causing the pending write.
摘要翻译：通常，本发明提供一种用于处理计算机程序的指令并用于指示指令属性和/或状态信息的系统和方法，使得可以增加处理系统的效率。在架构中，本发明的系统利用流水线，记分板和危险检测电路。流水线处理并执行计算机程序的指令。许多指令包括寄存器标识符，用于标识执行指令时应写入数据的寄存器。当执行指令之一产生的数据尚未写入由一个指令的寄存器标识符识别的寄存器，并且不能用于执行程序的其他指令时，一个指令的寄存器标识符被传送到记分板。记分板包括多个多位寄存器，并且多位寄存器之一中的第一位基于所接收的寄存器标识来改变。记分板还可以接收与该指令相关联的数据，并且可以基于所接收的数据改变该一个寄存器中的第二位。因此，记分板中的每个寄存器指示是否存在对特定寄存器的挂起写入，并且指示与引起挂起写入的指令相关联的信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式