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1. 发明授权

US06651164B1 System and method for detecting an erroneous data hazard between instructions of an instruction group and resulting from a compiler grouping error 有权
标题翻译：用于检测指令组的指令之间的错误数据危险并由编译器分组错误导致的系统和方法
公开(公告)号：US06651164B1
公开(公告)日：2003-11-18
申请号：US09418286
申请日：1999-10-14
申请人： Donald Charles Soltis, Jr. , Ronny Lee Arnold
发明人： Donald Charles Soltis, Jr. , Ronny Lee Arnold
IPC分类号： G06F1500
CPC分类号： G06F9/3853 , G06F9/3838
摘要： A superscalar processing system that detects data hazards within instruction groups transmitted to the processing system utilizes a content-addressable memory, a plurality of pipelines, an instruction dispersal unit (IDU), and a control mechanism. The IDU receives an instruction group that includes a plurality of instructions and transmits the instructions of the instruction group to the plurality of pipelines. The control mechanism stores register identifiers of the instructions in the content-addressable memory and determines whether a register identifier of one of the instructions is stored in the content-addressable memory. When the register identifier of the one instruction is stored in the content-addressable memory, the control mechanism transmits a warning signal indicating that one of the instruction groups contained a data hazard.
摘要翻译：检测发送到处理系统的指令组内的数据危害的超标量处理系统利用内容可寻址存储器，多个管线，指令分散单元（IDU）和控制机构。 IDU接收包括多个指令的指令组，并将指令组的指令发送到多个管线。所述控制机构将所述指令的寄存器标识符存储在所述内容寻址存储器中，并且确定所述指令之一的寄存器标识符是否存储在所述内容寻址存储器中。当一个指令的寄存器标识符存储在内容可寻址存储器中时，控制机构发送指示一个指令组包含数据危险的警告信号。

2. 发明授权

US06591393B1 Masking error detection/correction latency in multilevel cache transfers 有权
标题翻译：多级缓存传输中的掩码错误检测/校正延迟
公开(公告)号：US06591393B1
公开(公告)日：2003-07-08
申请号：US09507208
申请日：2000-02-18
申请人： Shawn Kenneth Walker , Dean A. Mulla , Donald Charles Soltis, Jr. , Terry L Lyon
发明人： Shawn Kenneth Walker , Dean A. Mulla , Donald Charles Soltis, Jr. , Terry L Lyon
IPC分类号： G11C2900
CPC分类号： G06F11/1064 , G06F12/0897
摘要： Methods and apparatus mask the latency of error detection and/or error correction applied to data transferred between a first memory and a second memory. The method comprises determining whether there is an error in a data unit in the first memory; transferring data based on the data unit from the first memory to a second memory, wherein the transferring step commences before completion of the determining step; and disabling at least part of the second memory if the determining step detects an error in the data unit. The disabling step may be accomplished, for example, by disabling the buffering of an address of the data unit or stalling the second memory.
摘要翻译：方法和装置掩盖应用于在第一存储器和第二存储器之间传送的数据的错误检测和/或纠错的等待时间。该方法包括确定第一存储器中的数据单元是否存在错误; 基于所述数据单元将数据从所述第一存储器传送到第二存储器，其中所述传送步骤在所述确定步骤完成之前开始; 以及如果所述确定步骤检测到所述数据单元中的错误，则禁用所述第二存储器的至少一部分。禁用步骤可以例如通过禁止缓冲数据单元的地址或停止第二存储器来实现。

3. 发明授权

US07243215B2 System and method for utilizing a scoreboard to indicate information pertaining to pending register writes 失效
标题翻译：用于利用记分板来指示关于挂起的注册写入的信息的系统和方法
公开(公告)号：US07243215B2
公开(公告)日：2007-07-10
申请号：US10648966
申请日：2003-08-27
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/3857
摘要： Generally, the present invention provides a system and method for processing instructions of a computer program and for indicating instruction attribute and/or status information so that the efficiency of the processing system may be increased. In architecture, the system of the present invention utilizes a pipeline, a scoreboard, and hazard detection circuitry. The pipeline processes and executes instructions of a computer program. Many of the instructions include register identifiers that identify registers where data should be written when the instructions are executed. When the data produced by execution of one of the instructions has yet to be written to the register identified by the one instruction's register identifier and is unavailable for use in executing other instructions of the program, the one instruction's register identifier is transmitted to the scoreboard. The scoreboard includes a plurality of multi-bit registers, and a first bit in one of the multi-bit registers is changed based on the received register identifier. The scoreboard also may receive data associated with the one instruction and may change a second bit in the one register based on the received data. Therefore, each register in the scoreboard indicates whether a pending write to a particular register exists and indicates information associated with the instruction causing the pending write.
摘要翻译：通常，本发明提供一种用于处理计算机程序的指令并用于指示指令属性和/或状态信息的系统和方法，使得可以增加处理系统的效率。在架构中，本发明的系统利用流水线，记分板和危险检测电路。流水线处理并执行计算机程序的指令。许多指令包括寄存器标识符，用于标识执行指令时应写入数据的寄存器。当执行指令之一产生的数据尚未写入由一个指令的寄存器标识符识别的寄存器，并且不能用于执行程序的其他指令时，一个指令的寄存器标识符被传送到记分板。记分板包括多个多位寄存器，并且多位寄存器之一中的第一位基于所接收的寄存器标识来改变。记分板还可以接收与该指令相关联的数据，并且可以基于所接收的数据改变该一个寄存器中的第二位。因此，记分板中的每个寄存器指示是否存在对特定寄存器的挂起写入，并且指示与引起挂起写入的指令相关联的信息。

4. 发明授权

US06728868B2 System and method for coalescing data utilized to detect data hazards 失效
标题翻译：用于检测数据危害的数据的系统和方法
公开(公告)号：US06728868B2
公开(公告)日：2004-04-27
申请号：US10282183
申请日：2002-10-28
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F934
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3867
摘要： The present invention generally relates to a processing system and method for coalescing instruction data to efficiently detect data hazards between instructions of a computer program. In architecture, the system of the present invention utilizes a plurality of pipelines, coalescing circuitry, and hazard detection circuitry. The plurality of pipelines is configured to process instructions of a computer program, and the coalescing circuitry is configured to receive, from the pipelines, a plurality of register identifiers identifying a plurality of registers. The coalescing circuitry is configured to coalesce said register identifiers thereby generating a coalesced register identifier identifying each of said plurality of registers. The hazard detection circuitry is configured to receive the coalesced register identifier and to perform a comparison of the coalesced register identifier with other information received from the pipelines. The hazard detection circuitry is further configured to detect a data hazard based on the comparison.
摘要翻译：本发明一般涉及一种用于聚合指令数据以有效地检测计算机程序的指令之间的数据危害的处理系统和方法。在架构中，本发明的系统利用多个管道，聚结电路和危害检测电路。多个管线被配置为处理计算机程序的指令，并且聚结电路被配置为从流水线接收识别多个寄存器的多个寄存器标识符。所述聚结电路被配置为聚结所述寄存器标识符，从而生成识别所述多个寄存器中的每一个的合并寄存器标识符。危险检测电路被配置为接收合并的寄存器标识符并执行合并的寄存器标识符与从管道接收的其他信息的比较。危害检测电路还被配置为基于比较来检测数据危害。

5. 发明授权

US07343479B2 Method and apparatus for implementing two architectures in a chip 失效
标题翻译：用于在芯片中实现两种架构的方法和装置
公开(公告)号：US07343479B2
公开(公告)日：2008-03-11
申请号：US10602916
申请日：2003-06-25
申请人： Patrick Knebel , Kevin David Safford , Donald Charles Soltis, Jr. , Joel D Lamb , Stephen R. Undy , Russell C Brockmann
发明人： Patrick Knebel , Kevin David Safford , Donald Charles Soltis, Jr. , Joel D Lamb , Stephen R. Undy , Russell C Brockmann
IPC分类号： G06F9/455
CPC分类号： G06F9/30174 , G06F9/30167 , G06F9/382 , G06F9/3853
摘要： The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexer or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.
摘要翻译：本发明是用于在单个芯片上实现两个架构的方法。该方法使用提取引擎来检索指令。如果指令是宏指令，则将宏指令解码为微指令，然后在仿真引擎内使用捆绑器捆绑这些微指令。捆绑包并行发布并分发到执行引擎并包含预解码位，以便执行引擎将它们视为微指令。在被传送到执行引擎之前，可以将指令保存在缓冲器中。该方法还可以通过使用多路复用器或其他方式，从模拟引擎的捆绑微指令和直接从获取引擎进行的本机微指令之间进行选择。本地微指令和捆绑的微指令都可以保存在缓冲区中。该方法还向执行引擎发送附加信息。

6. 发明授权

US06721875B1 Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form 失效
标题翻译：在处理器中实现单音节IP相关分支指令和长IP相关分支指令的方法和装置，其以束形式获取指令
公开(公告)号：US06721875B1
公开(公告)日：2004-04-13
申请号：US09510731
申请日：2000-02-22
申请人： James E McCormick, Jr. , Stephen R. Undy , Donald Charles Soltis, Jr.
发明人： James E McCormick, Jr. , Stephen R. Undy , Donald Charles Soltis, Jr.
IPC分类号： G06F1500
CPC分类号： G06F9/3853 , G06F9/322 , G06F9/324 , G06F9/328 , G06F9/3806 , G06F9/3844
摘要： Disclosed is a computer architecture with single-syllable IP-relative branch instructions and long IP-relative branch instructions (IP=instruction pointer). The architecture fetches instructions in multi-syllable, bundle form. Single-syllable IP-relative branch instructions occupy a single syllable in an instruction bundle, and long IP-relative branch instructions occupy two syllables in an instruction bundle. The additional syllable of the long branch carries with it additional IP-relative offset bits, which when merged with offset bits carried in a core branch syllable provide a much greater offset than is carried by a single-syllable branch alone. Thus, the long branch provides for greater reach within an address space. Use of the long branch to patch IA-64 architecture instruction bundles is also disclosed. Such a patch provides the reach of an indirect branch with the overhead of a single-syllable IP-relative branch.
摘要翻译：公开了具有单音节IP相关分支指令和长IP相对分支指令（IP =指令指针）的计算机体系结构。该体系结构以多音节，捆绑形式获取指令。单音节IP相对分支指令占用指令束中的单个音节，并且长IP相对分支指令占用指令束中的两个音节。长分支的附加音节带有附加的IP相对偏移位，当与核分支音节中携带的偏移位合并时，它提供比单音节单独承载的偏移更大的偏移。因此，长分支在地址空间内提供更大的覆盖。还公开了使用长分支来修补IA-64架构指令束。这样一个补丁提供了一个间接分支的触发与单音节IP相关分支的开销。

7. 发明授权

US06711671B1 Non-speculative instruction fetch in speculative processing 失效
标题翻译：投机处理中的非推测性指令提取
公开(公告)号：US06711671B1
公开(公告)日：2004-03-23
申请号：US09506773
申请日：2000-02-18
申请人： Stephen R. Undy , Donald Charles Soltis, Jr.
发明人： Stephen R. Undy , Donald Charles Soltis, Jr.
IPC分类号： G06F1500
CPC分类号： G06F9/3802 , G06F9/3842 , G06F9/3861
摘要： An apparatus for and a method of ensuring that a non-speculative instruction is not fetched into an execution pipeline, where the non-speculative instruction, if fetched, may cause a cache miss that causes potentially catastrophic speculative processing, e.g., speculative transfer of data from an I/O device. When a non-speculative instruction is scheduled for a fetch into the pipeline, a translation lookaside buffer (TLB) miss is made to occur, e.g., by preventing the lowest level TLB from storing any page table entry (PTE) associated with any of the non-speculative instructions. The TLB miss prevents the occurrence of any cache miss, and causes a micro-fault to be injected into the pipeline. The micro-fault includes an address corresponding to the subject non-speculative instruction, and when it reaches the end of the pipeline, causes a redirect of instruction flow of the pipeline to the address, and thus the non-speculative instruction is fetched and executed in a non-speculative manner.
摘要翻译：一种用于确保非推测性指令未被提取到执行流水线中的装置和方法，其中非推测性指令（如果获取）可能导致导致潜在灾难性投机处理的高速缓存未命中，例如数据的推测性传输从I / O设备。当调度非推测性指令以进入流水线时，会发生翻译后备缓冲区（TLB）未命中，例如，通过防止最低级TLB存储与任何一个非投机指示。 TLB错误防止任何高速缓存未命中的发生，并导致将微故障注入到管道中。微故障包括与主体非推测性指令对应的地址，并且当其到达流水线的末端时，导致流水线的指令流向该地址的重定向，从而取出并执行非推测性指令以不投机的方式。

8. 发明授权

US06711670B1 System and method for detecting data hazards within an instruction group of a compiled computer program 有权
标题翻译：在编译的计算机程序的指令组内检测数据危害的系统和方法
公开(公告)号：US06711670B1
公开(公告)日：2004-03-23
申请号：US09417582
申请日：1999-10-14
申请人： Donald Charles Soltis, Jr. , Ronny Lee Arnold
发明人： Donald Charles Soltis, Jr. , Ronny Lee Arnold
IPC分类号： G06F938
CPC分类号： G06F9/3853 , G06F9/3838
摘要： A superscalar processing system that detects data hazards within instruction groups utilizes a memory, a plurality of pipelines, an instruction dispersal unit (IDU), and a control mechanism. The memory includes a plurality of entries that respectively correspond with a plurality of registers. The IDU receives an instruction group that includes a plurality of instructions and transmits the instructions of the instruction group to the plurality of pipelines. The control mechanism analyzes one of the instructions and identifies an entry in the memory that corresponds with a register associated with the one instruction. The control mechanism then analyzes the entry and transmits a warning signal in response to a determination that the entry indicates that another instruction within the instruction group is associated with the register.
摘要翻译：检测指令组内的数据危害的超标量处理系统利用存储器，多个管线，指令分散单元（IDU）和控制机构。存储器包括分别对应于多个寄存器的多个条目。 IDU接收包括多个指令的指令组，并将指令组的指令发送到多个管线。控制机制分析其中一条指令，并识别存储器中与一条指令相关联的寄存器对应的条目。然后，控制机构响应确定该条目指示该指令组中的另一个指令与该寄存器相关联，分析该条目并发送一个警告信号。

9. 发明授权

US06618801B1 Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information 失效
标题翻译：用于使用包含微指令和模板信息的束来在芯片中实现两个架构的方法和装置
公开(公告)号：US06618801B1
公开(公告)日：2003-09-09
申请号：US09496845
申请日：2000-02-02
申请人： Patrick Knebel , Kevin David Safford , Donald Charles Soltis, Jr. , Joel D Lamb , Stephen R. Undy , Russell C Brockmann
发明人： Patrick Knebel , Kevin David Safford , Donald Charles Soltis, Jr. , Joel D Lamb , Stephen R. Undy , Russell C Brockmann
IPC分类号： G06F1500
CPC分类号： G06F9/30174 , G06F9/30167 , G06F9/382 , G06F9/3853
摘要： The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles those microinstructions using a bundler, within an emulation engine. The bundles are issued in parallel and dispatched to the execution engine and contain pre-decode bits so that the execution engine treats them as microinstructions. Before being transferred to the execution engine, the instructions may be held in a buffer. The method also selects between bundled microinstructions from the emulation engine and native microinstructions coming directly from the fetch engine, by using a multiplexor or other means. Both native microinstructions and bundled microinstructions may be held in the buffer. The method also sends additional information to the execution engine.
摘要翻译：本发明是用于在单个芯片上实现两个架构的方法。该方法使用提取引擎来检索指令。如果指令是宏指令，则将宏指令解码为微指令，然后在仿真引擎内使用捆绑器捆绑这些微指令。捆绑包并行发布并分发到执行引擎并包含预解码位，以便执行引擎将它们视为微指令。在被传送到执行引擎之前，可以将指令保存在缓冲器中。该方法还可以选择来自仿真引擎的捆绑微指令和直接来自取指引擎的本机微指令，通过使用多路复用器或其他方式。本地微指令和捆绑的微指令都可以保存在缓冲区中。该方法还向执行引擎发送附加信息。

10. 发明授权

US06604192B1 System and method for utilizing instruction attributes to detect data hazards 失效
标题翻译：利用指令属性来检测数据危害的系统和方法
公开(公告)号：US06604192B1
公开(公告)日：2003-08-05
申请号：US09490389
申请日：2000-01-24
申请人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
发明人： Ronny Lee Arnold , Donald Charles Soltis, Jr.
IPC分类号： G06F930
CPC分类号： G06F9/3867 , G06F9/3838 , G06F9/3857 , G06F9/3861
摘要： A computer system utilizing a processing system capable of efficiently comparing register identifiers and instruction attribute data to detect data hazards between instructions of a computer program is used to execute the computer program. The processing system utilizes at least one pipeline, a first decoder, a second decoder, and comparison logic. The pipeline receives and simultaneously processes instructions of a computer program. The first and second decoders are coupled to the pipeline and decode register identifiers associated with instructions being processed by the pipeline. The comparison logic is interfaced with the first and second decoders and receives the decoded register identifiers along with attribute data indicating the status and/or type of instructions being processed by the pipeline. The comparison logic compares the decoded register identifiers and the attribute data to other decoded register identifiers and attribute data to detect data hazards.
摘要翻译：使用能够有效地比较寄存器标识符和指令属性数据以检测计算机程序的指令之间的数据危害的处理系统的计算机系统来执行计算机程序。处理系统利用至少一个流水线，第一解码器，第二解码器和比较逻辑。管道接收并同时处理计算机程序的指令。第一和第二解码器耦合到流水线并解码与由管线正在处理的指令相关联的寄存器标识符。比较逻辑与第一和第二解码器接口并且接收解码的寄存器标识符以及指示由管线正在处理的指令的状态和/或类型的属性数据。比较逻辑将解码的寄存器标识符和属性数据与其他解码的寄存器标识符和属性数据进行比较，以检测数据危害。

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