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1. 发明授权

US06324674B2 Method and apparatus for parallel simultaneous global and detail routing 失效
标题翻译：并行同时全局和细节路由的方法和装置
公开(公告)号：US06324674B2
公开(公告)日：2001-11-27
申请号：US09062309
申请日：1998-04-17
申请人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
发明人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.
摘要翻译：一种用于在集成电路设计中布线网络的方法，所述方法包括以下步骤：将集成电路设计与沿第一方向和第二方向的线分开，形成具有顶点和边缘的路由图，其中顶点对应于第一方向上的线在第二方向上交叉线，将并行网络作为所述路由图的函数，并行处理器基本上同时运行，确定集成电路设计中的不同区域之间的相对电线拥塞，以及重新路由通过区域的网络电线拥塞比较高

2. 发明授权

US06253363B1 Net routing using basis element decomposition 失效
标题翻译：网络路由使用基元分解
公开(公告)号：US06253363B1
公开(公告)日：2001-06-26
申请号：US09062218
申请日：1998-04-17
申请人： Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic , Alexander E. Andreev
发明人： Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic , Alexander E. Andreev
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for routing a net on an integrated circuit device, said method comprising the steps of creating a list of basis elements of the net, said basis elements being defined by a predetermined size limitation, determining a complexity value for each basis element as a function of the distance between pins in the basis element, forming a hypertree for the net as a function of complexity values of basis elements so determined, and routing the net as a function of the hypertree.
摘要翻译：一种用于在集成电路设备上路由网络的方法，所述方法包括以下步骤：创建网络的基本元素的列表，所述基本元素由预定大小限制定义，将每个基元元素的复杂度值确定为函数在基元中的引脚之间的距离，形成网的强度作为如此确定的基本元素的复杂度的函数，并且将网作为强调函数来布线。

3. 发明授权

US06175950B1 Method and apparatus for hierarchical global routing descend 失效
标题翻译：分级全局路由下降的方法和装置
公开(公告)号：US06175950B1
公开(公告)日：2001-01-16
申请号：US09062217
申请日：1998-04-17
申请人： Ranko Scepanovic , Alexander E. Andreev , Elyar E. Gasanov , Pedja Raspopovic
发明人： Ranko Scepanovic , Alexander E. Andreev , Elyar E. Gasanov , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Net routing is optimized in an integrated circuit device by dividing an integrated circuit design with a first group of substantially parallel lines in a first direction and with a group of substantially parallel lines in a second direction, with the second direction being substantially perpendicular to the first direction. A first routing graph is formed with vertices corresponding to locations where lines in the first direction and lines in the second direction cross, and nets are globally routed as a function of the first routing graph. The integrated circuit design is further subdivided with a second group of substantially parallel lines in the first direction, and a second routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in the first direction cross lines in the group of substantially parallel lines in the second direction. For a net globally routed using the first routing graph, a first local net is formed in a first fragment of the second routing graph, and the first local net is rerouted within the first fragment by computing edge penalty values for edges in the first fragment and rerouting the first local net as a function of the edge penalty values.
摘要翻译：通过将集成电路设计与第一方向上的第一组基本上平行的线分隔开并且在第二方向上与一组基本上平行的线分开，使得第二方向基本上垂直于第一方向方向。第一路由图形成为与第一方向上的线和第二方向上的线交叉的位置相对应的顶点，并且网络作为第一路由图的函数被全局路由。集成电路设计在第一方向上被进一步细分为第二组基本上平行的线，并且第二路由图形成为与第一方向交叉线上的基本上平行的第一组和第二组中的线对应的顶点在第二方向上基本平行的线组。对于使用第一路由图全局路由的网络，在第二路由图的第一片段中形成第一本地网，并且通过计算第一片段中的边缘的边缘惩罚值，在第一片段内重新路由第一本地网，作为边缘惩罚值的函数重新路由第一个本地网络。

4. 发明授权

US06845495B2 Multidirectional router 失效
标题翻译：多向路由器
公开(公告)号：US06845495B2
公开(公告)日：2005-01-18
申请号：US10027642
申请日：2001-12-20
申请人： Alexandre E. Andreev , Elyar E. Gasanov , Ranko Scepanovic
发明人： Alexandre E. Andreev , Elyar E. Gasanov , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention is directed to a system and method for providing multidirectional routing. The present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.
摘要翻译：本发明涉及用于提供多向路由的系统和方法。本发明可以在这些层中的每一层上提供任意数量的路由层和任意方向，以提供更小的管芯尺寸，并通过为网络布线方向提供更多的灵活性来降低功耗。

5. 发明授权

US08527851B2 System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors 有权
标题翻译：用于实现可变数量错误的可配置二进制Bose-Chaudhuri-Hocquenghem（BCH）编码器的通用多极的系统和方法
公开(公告)号：US08527851B2
公开(公告)日：2013-09-03
申请号：US12221484
申请日：2008-08-04
申请人： Alexander E. Andreev , Elyar E. Gasanov , Pavel Aliseychik , Ilya Neznanov , Pavel Panteleev
发明人： Alexander E. Andreev , Elyar E. Gasanov , Pavel Aliseychik , Ilya Neznanov , Pavel Panteleev
IPC分类号： H03M13/00
CPC分类号： H03M13/152 , H03M13/6516
摘要： The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.
摘要翻译：本发明是具有可变数量的错误的可配置二进制BCH编码器。编码器可以实现通用多极块，其可以被配置为用于接收错误号输入，其可以包括编码器的最大误差数限制，以及用于基于错误数输入来计算多个误差系数。编码器还可以被配置为用于接收信息字的多个信息位。编码器还可以被配置为用于发送/输出信息比特的第一（未修改）子集作为编码器输出。编码器还可以被配置为基于信息位的第二子集和误差系数来计算多个奇偶校验位。编码器可以被进一步配置为发送/输出计算的奇偶校验位作为编码器输出的一部分。

6. 发明申请

US20100031126A1 System and method for using the universal multipole for the implementation of a configurable binary bose-chaudhuri-hocquenghem (BCH) encoder with variable number of errors 有权
标题翻译：用于实现可变数目错误的可配置二进制bose-chaudhuri-hocquenghem（BCH）编码器的通用多极的系统和方法
公开(公告)号：US20100031126A1
公开(公告)日：2010-02-04
申请号：US12221484
申请日：2008-08-04
申请人： Alexander E. Andreev , Elyar E. Gasanov , Pavel Aliseychik , Ilya Neznanov , Pavel Panteleev
发明人： Alexander E. Andreev , Elyar E. Gasanov , Pavel Aliseychik , Ilya Neznanov , Pavel Panteleev
IPC分类号： H03M13/00
CPC分类号： H03M13/152 , H03M13/6516
摘要： The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.
摘要翻译：本发明是具有可变数量的错误的可配置二进制BCH编码器。编码器可以实现通用多极块，其可以被配置为用于接收错误号输入，其可以包括编码器的最大误差数限制，以及用于基于错误数输入来计算多个误差系数。编码器还可以被配置为用于接收信息字的多个信息位。编码器还可以被配置为用于发送/输出信息比特的第一（未修改）子集作为编码器输出。编码器还可以被配置为基于信息位的第二子集和误差系数来计算多个奇偶校验位。编码器可以被进一步配置为发送/输出计算的奇偶校验位作为编码器输出的一部分。

7. 发明授权

US08868890B2 No-delay microsequencer 有权
标题翻译：无延迟微定序器
公开(公告)号：US08868890B2
公开(公告)日：2014-10-21
申请号：US13106119
申请日：2011-05-12
申请人： Yurii S. Shutkin , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Pavel A. Panteleev
发明人： Yurii S. Shutkin , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Pavel A. Panteleev
IPC分类号： G06F9/30 , G06F9/32
CPC分类号： G06F9/322 , G06F9/30054 , G06F9/30065
摘要： An apparatus generally including a memory and a circuit is disclosed. The memory may be configured to store a plurality of instructions. Each of the instructions generally includes a corresponding command and a corresponding command repeat count. At least one of the instructions may include a subprocedure call. The circuit may be configured to (i) decode the instructions one at a time and (ii) present a sequence of the commands at an interface. The sequence (i) may be based on the decoding and (ii) may have no delays between consecutive the commands at the interface.
摘要翻译：通常包括存储器和电路的装置被公开。存储器可以被配置为存储多个指令。每个指令通常包括相应的命令和相应的命令重复计数。指令中的至少一个可以包括子过程调用。电路可以被配置为（i）一次解码指令，以及（ii）在接口处呈现一系列命令。序列（i）可以基于解码，并且（ii）在接口的连续命令之间可以没有延迟。

8. 发明授权

US08842784B2 L-value generation in a decoder 有权
标题翻译：解码器中的L值生成
公开(公告)号：US08842784B2
公开(公告)日：2014-09-23
申请号：US13115359
申请日：2011-05-25
申请人： Andrey P. Sokolov , Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Yurii S. Shutkin
发明人： Andrey P. Sokolov , Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Yurii S. Shutkin
IPC分类号： H03M13/03 , H03M13/00 , H03M13/39 , H03M13/29
CPC分类号： H03M13/296 , H03M13/3927 , H03M13/3988 , H03M13/6525 , H03M13/6544
摘要： An apparatus having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may be configured to generate a plurality of load values corresponding to a trellis of a decoding process. The second circuit generally includes a plurality of calculation layers. The calculation layers may be configured to generate a plurality of maximum values in response to the load values. The third circuit may be configured to generate a plurality of L-values of the decoding process in response to the maximum values.
摘要翻译：公开了一种具有第一电路，第二电路和第三电路的装置。第一电路可以被配置为产生对应于解码处理格架的多个负载值。第二电路通常包括多个计算层。计算层可以被配置为响应于负载值产生多个最大值。第三电路可以被配置为响应于最大值产生解码处理的多个L值。

9. 发明授权

US08621329B2 Reconfigurable BCH decoder 有权
标题翻译：可重构BCH解码器
公开(公告)号：US08621329B2
公开(公告)日：2013-12-31
申请号：US13044809
申请日：2011-03-10
申请人： Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Yurii S. Shutkin
发明人： Pavel A. Panteleev , Elyar E. Gasanov , Ilya V. Neznanov , Andrey P. Sokolov , Yurii S. Shutkin
IPC分类号： H03M13/00
CPC分类号： H03M13/6516 , H03M13/152 , H03M13/1525 , H03M13/6561
摘要： An apparatus generally having a port, a first circuit and a second circuit is disclosed. The port may be configured to receive a current length of a codeword. The current length may be less than a maximum length of the codeword that the apparatus is designed to decode. The first circuit may be configured to calculate in parallel (i) a sequence of intermediate syndromes from the codeword and (ii) a sequence of correction values based on the current length. The second circuit may be configured to generate a particular number of updated syndromes by modifying the intermediate syndromes with the correction values. The particular number is generally twice a maximum error limit of the codeword.
摘要翻译：公开了一种通常具有端口，第一电路和第二电路的装置。端口可以被配置为接收码字的当前长度。当前长度可以小于设备被设计为解码的码字的最大长度。第一电路可以被配置为并行计算（i）来自码字的中间综合征序列，以及（ii）基于当前长度的校正值序列。第二电路可以被配置为通过用修正值修改中间综合征来生成特定数量的更新的综合征。特定数字通常是码字的最大误差限制的两倍。

10. 发明申请

US20110239079A1 PROGRAMMABLE CIRCUIT FOR HIGH SPEED COMPUTATION OF THE INTERLEAVER TABLES FOR MULTIPLE WIRELESS STANDARDS 有权
标题翻译：用于多个无线标准的交互表的高速计算的可编程电路
公开(公告)号：US20110239079A1
公开(公告)日：2011-09-29
申请号：US12894458
申请日：2010-09-30
申请人： Andrey P. Sokolov , Elyar E. Gasanov , Ilya V. Neznanov , Pavel A. Aliseychik , Pavel A. Panteleev
发明人： Andrey P. Sokolov , Elyar E. Gasanov , Ilya V. Neznanov , Pavel A. Aliseychik , Pavel A. Panteleev
IPC分类号： H03M13/27 , G06F11/10
CPC分类号： H03M13/2771 , H03M13/2767 , H03M13/6519 , H04L1/005 , H04L1/0066 , H04L1/0071
摘要： A circuit having a first circuit and a memory is disclosed. The first circuit may be configured to (i) receive a control signal that identifies a current one of a plurality of wireless communication standards and a code word size and (ii) generate a plurality of tables corresponding to both the current wireless communication standard and the code word size. Each of the tables generally has a plurality of indices. Up to two of the indices may be generated by the first circuit per clock cycle. Each of the tables generally comprises a permutation table of a turbo code interleaver. The memory may be configured to store the tables.
摘要翻译：公开了具有第一电路和存储器的电路。第一电路可以被配置为（i）接收识别多个无线通信标准中的当前一个无线通信标准和码字大小的控制信号，并且（ii）生成与当前无线通信标准和代码字大小。每个表格通常具有多个索引。每个时钟周期最多可以由第一个电路产生两个索引。每个表通常包括turbo码交织器的置换表。可以将存储器配置为存储表。

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