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1. 发明授权

US09653620B2 Semiconductor device 有权
公开(公告)号：US09653620B2
公开(公告)日：2017-05-16
申请号：US14932538
申请日：2015-11-04
申请人： Alexander Dietrich Hölke , Deb Kumar Pal , Kia Yaw Kee , Yang Hao
发明人： Alexander Dietrich Hölke , Deb Kumar Pal , Kia Yaw Kee , Yang Hao
IPC分类号： H01L29/868 , H01L29/40 , H01L29/861
CPC分类号： H01L29/868 , H01L29/405 , H01L29/407 , H01L29/8611
摘要： A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.

2. 发明授权

US09202937B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09202937B2
公开(公告)日：2015-12-01
申请号：US13321960
申请日：2010-05-14
申请人： Alexander Dietrich Hölke , Deb Kumar Pal , Kia Yaw Kee , Hao Yang
发明人： Alexander Dietrich Hölke , Deb Kumar Pal , Kia Yaw Kee , Hao Yang
IPC分类号： H01L29/861 , H01L29/40
CPC分类号： H01L29/868 , H01L29/405 , H01L29/407 , H01L29/8611
摘要： A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions.
摘要翻译：一种半导体器件，包括：p或p +掺杂部分; 通过半导体漂移部分从p或p +掺杂部分分离的n或n +掺杂部分; 在所述漂移部分和所述至少一个掺杂部分相遇的区域中邻近所述漂移部分设置的绝缘部分和所述掺杂部分中的至少一个; 以及至少一个附加部分，其被设置为当在掺杂部分之间施加电压差时，显着地减小所述区域中的电场强度的变化。

3. 发明申请

US20120161276A1 SEMICONDUCTOR DEVICE COMPRISING AN ISOLATION TRENCH INCLUDING SEMICONDUCTOR ISLANDS 有权
标题翻译：包含半导体岛的隔离层的半导体器件
公开(公告)号：US20120161276A1
公开(公告)日：2012-06-28
申请号：US13321867
申请日：2009-05-22
申请人： Deb Kumar Pal , Alexander Hoelke , Pei Shan Chua , Gopalakrishnan Kulathu Sankar , Kia Yaw Kee , Yang Hao , Uta Kuniss
发明人： Deb Kumar Pal , Alexander Hoelke , Pei Shan Chua , Gopalakrishnan Kulathu Sankar , Kia Yaw Kee , Yang Hao , Uta Kuniss
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/868 , H01L29/405 , H01L29/407 , H01L29/8611
摘要： The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.
摘要翻译：本发明提供了半导体器件及其制造方法，其中漂移区的优良电介质终端由具有中间半导体岛的多个相交沟槽完成。因此，可以实现深沟槽布置，而不受隔离结构的整体宽度的限制。

4. 发明申请

US20160056305A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160056305A1
公开(公告)日：2016-02-25
申请号：US14932538
申请日：2015-11-04
申请人： Alexander Dietrich Holke , Deb Kumar Pal , Kia Yaw Kee , Yang Hao
发明人： Alexander Dietrich Holke , Deb Kumar Pal , Kia Yaw Kee , Yang Hao
IPC分类号： H01L29/868 , H01L29/40
CPC分类号： H01L29/868 , H01L29/405 , H01L29/407 , H01L29/8611
摘要： A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and the at least one doped portion meet. The device further includes at least one additional portion, wherein the at least one additional portion is located such that, when the doped portions and the at least one additional portion are biased, the electrical potential lines leave the semiconductor drift portion homogeneously.
摘要翻译：一种包括p或p +掺杂部分和通过半导体漂移部分从p或p +掺杂部分分离的n或n +掺杂部分的半导体器件。该装置还包括邻近漂移部分设置的绝缘部分和漂移部分和至少一个掺杂部分相交的区域中的至少一个掺杂部分。器件还包括至少一个附加部分，其中至少一个附加部分被定位成使得当掺杂部分和至少一个附加部分被偏置时，电势线均匀地离开半导体漂移部分。

5. 发明授权

US08841186B2 Manufacturing of a semiconductor device and corresponding semiconductor device 有权
标题翻译：制造半导体器件和相应的半导体器件
公开(公告)号：US08841186B2
公开(公告)日：2014-09-23
申请号：US13582142
申请日：2010-03-04
申请人： Alexander Hoelke , Deb Kumar Pal , Kia Yaw Kee , Yang Hao
发明人： Alexander Hoelke , Deb Kumar Pal , Kia Yaw Kee , Yang Hao
IPC分类号： H01L21/336 , H01L29/78 , H01L29/06 , H01L29/10 , H01L21/265 , H01L29/66 , H01L29/423
CPC分类号： H01L21/26586 , H01L29/0634 , H01L29/0696 , H01L29/1033 , H01L29/4236 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29). A semiconductor device (12) comprises at least one trench (22) for a gate (42) of the semiconductor device (12); and a body (44) having at least one wall (33) of the at least one trench (22), wherein a deviation (64) of a doping concentration (62) along a distance (66) in depth-direction (do) of the at least one trench (22) in a surface (33) of the at least one wall (33) is less than ten percent of a maximum value (68) of the doping concentration (62) along the distance (66).
摘要翻译：所公开的制造（110,120,130,140）半导体器件（12）的方法具有以下步骤：形成半导体器件的主体（44）的至少一个壁（33）（12）通过将用于半导体器件（12）的栅极（42）的至少一个沟槽（22）蚀刻到主体（44）中; 以及在所述至少一个沟槽（22）的所述蚀刻（112）之后并且在涂覆所述至少一个沟槽（22）之前，在所述主体（44）的所述至少一个壁（33）中执行倾斜注入掺杂（126,128）具有绝缘层（29）的沟槽（22）。半导体器件（12）包括用于半导体器件（12）的栅极（42）的至少一个沟槽（22）; 以及具有所述至少一个沟槽（22）的至少一个壁（33）的主体（44），其中沿着深度方向（do）的距离（66）的掺杂浓度（62）的偏差（64）在所述至少一个壁（33）的表面（33）中的所述至少一个沟槽（22）的距离小于所述距离（66）的所述掺杂浓度（62）的最大值（68）的百分之十。

6. 发明授权

US08759942B2 Semiconductor device comprising an isolation trench including semiconductor islands 有权
标题翻译：半导体器件包括包括半导体岛的隔离沟槽
公开(公告)号：US08759942B2
公开(公告)日：2014-06-24
申请号：US13321867
申请日：2009-05-22
申请人： Alexander Hoelke , Deb Kumar Pal , Pei Shan Chua , Gopalakrishnan Kulathu Sankar , Kia Yaw Kee , Yang Hao , Uta Kuniss
发明人： Alexander Hoelke , Deb Kumar Pal , Pei Shan Chua , Gopalakrishnan Kulathu Sankar , Kia Yaw Kee , Yang Hao , Uta Kuniss
IPC分类号： H01L21/70 , H01L21/76 , H01L29/40 , H01L29/861
CPC分类号： H01L29/868 , H01L29/405 , H01L29/407 , H01L29/8611
摘要： The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.
摘要翻译：本发明提供了半导体器件及其制造方法，其中漂移区的优良电介质终端由具有中间半导体岛的多个相交沟槽完成。因此，可以实现深沟槽布置，而不受隔离结构的整体宽度的限制。

7. 发明申请

US20120319193A1 MANUFACTURING OF A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造和相应的半导体器件
公开(公告)号：US20120319193A1
公开(公告)日：2012-12-20
申请号：US13582142
申请日：2010-03-04
申请人： Alexander Hoelke , Deb Kumar Pal , Kia Yaw Kee , Yang Hao
发明人： Alexander Hoelke , Deb Kumar Pal , Kia Yaw Kee , Yang Hao
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26586 , H01L29/0634 , H01L29/0696 , H01L29/1033 , H01L29/4236 , H01L29/66659 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29). A semiconductor device (12) comprises at least one trench (22) for a gate (42) of the semiconductor device (12); and a body (44) having at least one wall (33) of the at least one trench (22), wherein a deviation (64) of a doping concentration (62) along a distance (66) in depth-direction (do) of the at least one trench (22) in a surface (33) of the at least one wall (33) is less than ten percent of a maximum value (68) of the doping concentration (62) along the distance (66).
摘要翻译：所公开的制造（110,120,130,140）半导体器件（12）的方法具有以下步骤：形成半导体器件的主体（44）的至少一个壁（33）（12）通过将用于半导体器件（12）的栅极（42）的至少一个沟槽（22）蚀刻到主体（44）中; 以及在所述至少一个沟槽（22）的所述蚀刻（112）之后并且在涂覆所述至少一个沟槽（22）之前，在所述主体（44）的所述至少一个壁（33）中执行倾斜注入掺杂（126,128）具有绝缘层（29）的沟槽（22）。半导体器件（12）包括用于半导体器件（12）的栅极（42）的至少一个沟槽（22）; 以及具有所述至少一个沟槽（22）的至少一个壁（33）的主体（44），其中沿着深度方向（do）的距离（66）的掺杂浓度（62）的偏差（64）在所述至少一个壁（33）的表面（33）中的所述至少一个沟槽（22）的距离小于所述距离（66）的所述掺杂浓度（62）的最大值（68）的百分之十。

8. 发明申请

US20120126377A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120126377A1
公开(公告)日：2012-05-24
申请号：US13321960
申请日：2010-05-14
申请人： Alexander Dietrich Holke , Deb Kumar Pal , Kia Yaw Kee , Hao Yang
发明人： Alexander Dietrich Holke , Deb Kumar Pal , Kia Yaw Kee , Hao Yang
IPC分类号： H01L29/02
CPC分类号： H01L29/868 , H01L29/405 , H01L29/407 , H01L29/8611
摘要： A semiconductor device comprising: a p or p+ doped portion; an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion; an insulating portion provided adjacent the drift portion and at least one of the doped portions in a region where the drift portion and said at least one doped portion meet; and at least one additional portion which is arranged for significantly reducing the variation of the electric field strength in said region when a voltage difference is applied between the doped portions.
摘要翻译：一种半导体器件，包括：p或p +掺杂部分; 通过半导体漂移部分从p或p +掺杂部分分离的n或n +掺杂部分; 在所述漂移部分和所述至少一个掺杂部分相遇的区域中邻近所述漂移部分设置的绝缘部分和所述掺杂部分中的至少一个; 以及至少一个附加部分，其被设置为当在掺杂部分之间施加电压差时，显着地减小所述区域中的电场强度的变化。

9. 发明申请

US20110198690A1 TRANSISTOR 有权
标题翻译：晶体管
公开(公告)号：US20110198690A1
公开(公告)日：2011-08-18
申请号：US12867257
申请日：2009-02-12
申请人： Yong Hai Hu , Elizabeth Ching Tee Kho , Zheng Chao Liu , Deb Kumar Pal , Michael Mee Gouh Tiong , Jian Liu , Kia Yaw Kee , William Siang Lim Lau
发明人： Yong Hai Hu , Elizabeth Ching Tee Kho , Zheng Chao Liu , Deb Kumar Pal , Michael Mee Gouh Tiong , Jian Liu , Kia Yaw Kee , William Siang Lim Lau
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L29/0653 , H01L29/42368 , H01L29/7835
摘要： A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.
摘要翻译：一种金属氧化物半导体（MOS）晶体管，包括：源极; 一个门以及漏极，源极，栅极和漏极位于位于衬底中或衬底上的第一掺杂极性的阱结构中或其上; 其中所述源极和漏极中的至少一个包括第一结构，所述第一结构包括：形成第一漂移区的第一区，所述第一区具有与所述第一掺杂极性相反的第二掺杂极性; 所述第二区域是所述第二区域中的第二掺杂极性的第二区域，所述第二区域是阱区域，并且具有高于所述第一区域的掺杂浓度的掺杂浓度; 以及在第二区域中或第二区域上的第二掺杂极性的第三区域。由于存在第二区域，与不具有第二区域的类似晶体管相比，晶体管可能具有较低的导通电阻。击穿电压可能仅在很小程度上受到影响。

10. 发明授权

US09748383B2 Transistor 有权
公开(公告)号：US09748383B2
公开(公告)日：2017-08-29
申请号：US12867257
申请日：2009-02-12
申请人： Elizabeth Ching Tee Kho , Zheng Chao Liu , Deb Kumar Pal , Michael Mee Gouh Tiong , Jian Liu , Kia Yaw Kee
发明人： Yong Hai Hu , Elizabeth Ching Tee Kho , Zheng Chao Liu , Deb Kumar Pal , Michael Mee Gouh Tiong , Jian Liu , Kia Yaw Kee , William Lau
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423
CPC分类号： H01L29/7834 , H01L29/0653 , H01L29/42368 , H01L29/7835
摘要： A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.

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