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1. 发明授权

US08918752B2 Determining alignment using a spatially varying charge distribution 有权
标题翻译：使用空间变化的电荷分布确定对准
公开(公告)号：US08918752B2
公开(公告)日：2014-12-23
申请号：US13326301
申请日：2011-12-14
申请人： Alex Chow , Robert J. Drost , Ronald Ho , Robert D. Hopkins , Ivan E. Sutherland
发明人： Alex Chow , Robert J. Drost , Ronald Ho , Robert D. Hopkins , Ivan E. Sutherland
IPC分类号： G06F17/50
CPC分类号： H01L23/585 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/72 , H01L25/0657 , H01L2224/13021 , H01L2224/131 , H01L2224/16145 , H01L2224/16147 , H01L2224/292 , H01L2224/293 , H01L2224/32145 , H01L2224/83851 , H01L2225/06531 , H01L2225/06593 , H01L2924/014 , H01L2924/00014
摘要： A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a spatial alignment in more than one direction between the semiconductor die and another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies and/or an angular alignment of the semiconductor dies to be determined.
摘要翻译：描述半导体管芯。该半导体管芯包括驱动器和电耦合到驱动器并且靠近半导体管芯的表面的空间对准换能器。驱动器在空间对准转换器中在至少一个方向上建立空间变化的电荷分布，从而有助于确定半导体管芯和另一个半导体管芯之间的多于一个方向上的空间对准。特别地，靠近另一个半导体管芯的表面的空间对准传感器可以检测与空间变化的电荷分布相关联的电场（或相关的静电电位）。该检测的电场可以允许确定半导体管芯的表面之间的垂直间隔和/或半导体管芯的角度对准。

2. 发明申请

US20130154608A1 DETERMINING ALIGNMENT USING A SPATIALLY VARYING CHARGE DISTRIBUTION 有权
标题翻译：使用空间变化的充电分配来确定对齐
公开(公告)号：US20130154608A1
公开(公告)日：2013-06-20
申请号：US13326301
申请日：2011-12-14
申请人： Alex Chow , Robert J. Drost , Ronald Ho , Robert D. Hopkins , Ivan E. Sutherland
发明人： Alex Chow , Robert J. Drost , Ronald Ho , Robert D. Hopkins , Ivan E. Sutherland
IPC分类号： G01N27/00 , H01L23/58
CPC分类号： H01L23/585 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/72 , H01L25/0657 , H01L2224/13021 , H01L2224/131 , H01L2224/16145 , H01L2224/16147 , H01L2224/292 , H01L2224/293 , H01L2224/32145 , H01L2224/83851 , H01L2225/06531 , H01L2225/06593 , H01L2924/014 , H01L2924/00014
摘要： A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a spatial alignment in more than one direction between the semiconductor die and another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies and/or an angular alignment of the semiconductor dies to be determined.
摘要翻译：描述半导体管芯。该半导体管芯包括驱动器和电耦合到驱动器并且靠近半导体管芯的表面的空间对准换能器。驱动器在空间对准转换器中在至少一个方向上建立空间变化的电荷分布，从而有助于确定半导体管芯和另一个半导体管芯之间的多于一个方向上的空间对准。特别地，靠近另一个半导体管芯的表面的空间对准传感器可以检测与空间变化的电荷分布相关联的电场（或相关的静电电位）。该检测的电场可以允许确定半导体管芯的表面之间的垂直间隔和/或半导体管芯的角度对准。

3. 发明授权

US07200830B2 Enhanced electrically-aligned proximity communication 有权
标题翻译：增强的电对齐邻近通信
公开(公告)号：US07200830B2
公开(公告)日：2007-04-03
申请号：US10879607
申请日：2004-06-28
申请人： Robert J. Drost , Ivan E. Sutherland , Ronald Ho
发明人： Robert J. Drost , Ivan E. Sutherland , Ronald Ho
IPC分类号： G06F17/50
CPC分类号： H01L23/48 , H01L25/0657 , H01L2225/06531 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates capacitive inter-chip communication. During operation, the system first determines an alignment between a first semiconductor die and a second semiconductor die. Next, electrical signals are selectively routed to at least one interconnect pad in a plurality of interconnect pads based on the alignment thereby facilitating communication between the first semiconductor die and the second semiconductor die. The plurality of interconnect pads can include transmitting pads, receiving pads, and transmitting and receiving pads. The alignment may be determined continuously or at times separated by an interval, where the interval is fixed or variable. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种便于电容芯片间通信的系统。在操作期间，系统首先确定第一半导体管芯和第二半导体管芯之间的对准。接下来，基于对准，电信号被选择性地路由到多个互连焊盘中的至少一个互连焊盘，从而便于第一半导体管芯和第二半导体管芯之间的连通。多个互连焊盘可以包括传输焊盘，接收焊盘以及发射和接收焊盘。可以连续地或有时间隔地间隔地确定对准，其中间隔是固定的或可变的。提供了该实施例的几个变型。

4. 发明授权

US07046017B1 Full-wave rectifier for capacitance measurements 有权
标题翻译：全波整流电容测量
公开(公告)号：US07046017B1
公开(公告)日：2006-05-16
申请号：US11216754
申请日：2005-08-30
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01R27/26 , G01N27/22
CPC分类号： G01R27/2605
摘要： One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种用于测量电容的电子电路和方法。信号发生机构在电容的一个端子上产生具有预定频率和预定义的低和高电压电平的信号。电容的另一个端子耦合到开关机构。开关机构被设置为将电容的另一个端子耦合到每个信号周期的一部分的第一放大器或第二放大器，由此对在电容中的两个端子之间流动的瞬态电流进行全波整流。第一放大器和第二放大器的输出耦合到用于测量电流的电流测量机构。电容由测量电流确定。提供了该实施例的几个变型。

5. 发明授权

US06987394B1 Full-wave rectifier for capacitance measurements 有权
公开(公告)号：US06987394B1
公开(公告)日：2006-01-17
申请号：US10879608
申请日：2004-06-28
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01R27/26
CPC分类号： G01R27/2605
摘要： One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.

6. 发明授权

US07026867B2 Floating input amplifier for capacitively coupled communication 有权
标题翻译：用于电容耦合通信的浮动输入放大器
公开(公告)号：US07026867B2
公开(公告)日：2006-04-11
申请号：US10879606
申请日：2004-06-28
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： H03F1/02
CPC分类号： H03F3/45977 , H03F3/08
摘要： One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.
摘要翻译：本发明的一个实施例提供一种具有不具有直流耦合的输入的电容耦合接收放大器。在输入端编程一个直流电压。在编程期间，发射机被保持在表示逻辑“1”的电压和表示逻辑“0”的电压之间的中点处的电压，并且接收机放大器的输入电压被编程为基本上是切换阈值接收放大器的电压。然后，在正常数据通信期间，发射机驱动耦合到接收放大器的高电平和低电信号。由于接收机放大器的输入已基本设置为直流电压，所以接收放大器不需要控制电信号中每个转换的输入的直流电压。

7. 发明授权

US07786427B2 Proximity optical memory module having an electrical-to-optical and optical-to-electrical converter 有权
标题翻译：接近光学存储器模块，其具有电 - 光和光 - 电转换器
公开(公告)号：US07786427B2
公开(公告)日：2010-08-31
申请号：US12115989
申请日：2008-05-06
申请人： Craig S. Forrest , Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Craig S. Forrest , Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01J1/04
CPC分类号： G11C5/04 , G11C5/143 , G11C7/1051 , G11C7/1054 , G11C7/1078 , G11C7/1081 , H01L23/48 , H01L23/642 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/167 , H01L2225/06562 , H01L2924/01067 , H01L2924/14 , H01L2924/19041
摘要： A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.
摘要翻译：存储器模块由多个存储器芯片和固定在基板上的光学接口芯片形成。芯片通过邻近通信（PxC）相互连接，其中每个芯片包括发射和接收元件，例如当芯片彼此面对放置在一起时形成电容耦合链路的电焊盘。 PxC链路可以直接在芯片之间或通过中间无源桥芯片。接口芯片耦合到外部光通道并且包括用于与存储器芯片通信的光学和电信号之间的转换器，控制电路，缓冲器和PxC元件。存储器阵列可以是形成冗余PxC网络的接口芯片周围的线性或二维阵列，可选地具有冗余PxC连接。多个矩形存储器芯片可以将它们的窄边呈现给接口芯片以最大化带宽。

8. 发明申请

US20090279341A1 PROXIMITY OPTICAL MEMORY MODULE 有权
标题翻译：临近光学存储模块
公开(公告)号：US20090279341A1
公开(公告)日：2009-11-12
申请号：US12115989
申请日：2008-05-06
申请人： Craig S. Forrest , Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Craig S. Forrest , Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C5/143 , G11C7/1051 , G11C7/1054 , G11C7/1078 , G11C7/1081 , H01L23/48 , H01L23/642 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/167 , H01L2225/06562 , H01L2924/01067 , H01L2924/14 , H01L2924/19041
摘要： A memory module is formed of multiple memory chips and an optical interface chip fixed on a substrate. The chips are interconnected by proximity communication (PxC) in which each chip includes transmitting and receiving elements, such as electrical pads which form capacitively coupled links when the chips are placed together with their pads facing each other. The PxC links may be directly between the chips or through an intermediate passive bridge chip. The interface chip is coupled to an external optical channel and includes converters between optical and electrical signals, control circuitry, buffers, and PxC elements for communicating with the memory chips. The array of memories may be a linear or two-dimensional array around the interface chip forming a redundant PxC network, optionally with redundant PxC connections. Multiple rectangular memory chips may present their narrow sides to the interface chip to maximize bandwidth.
摘要翻译：存储器模块由多个存储器芯片和固定在基板上的光学接口芯片形成。芯片通过邻近通信（PxC）相互连接，其中每个芯片包括发射和接收元件，例如当芯片彼此面对放置在一起时形成电容耦合链路的电焊盘。 PxC链路可以直接在芯片之间或通过中间无源桥芯片。接口芯片耦合到外部光通道并且包括用于与存储器芯片通信的光学和电信号之间的转换器，控制电路，缓冲器和PxC元件。存储器阵列可以是形成冗余PxC网络的接口芯片周围的线性或二维阵列，可选地具有冗余PxC连接。多个矩形存储器芯片可以将它们的窄边呈现给接口芯片以最大化带宽。

9. 发明授权

US06753726B1 Apparatus and method for an offset-correcting sense amplifier 有权
公开(公告)号：US06753726B1
公开(公告)日：2004-06-22
申请号：US10356450
申请日：2003-01-31
申请人： Robert J. Drost , Ivan E. Sutherland
发明人： Robert J. Drost , Ivan E. Sutherland
IPC分类号： G06G712
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H03F1/301 , H03F1/342 , H01L2924/00
摘要： An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.

10. 发明授权

US06710436B1 Method and apparatus for electrostatically aligning integrated circuits 有权
公开(公告)号：US06710436B1
公开(公告)日：2004-03-23
申请号：US10317481
申请日：2002-12-12
申请人： David L. Harris , Robert J. Drost , Ivan E. Sutherland
发明人： David L. Harris , Robert J. Drost , Ivan E. Sutherland
IPC分类号： B65G4907
CPC分类号： H01L24/95 , H01L23/50 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2223/6622 , H01L2224/13012 , H01L2224/81121 , H01L2224/81801 , H01L2224/95145 , H01L2225/06527 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01039 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/0401
摘要： One embodiment of the present invention provides a system that uses electrostatic forces to align semiconductor chips relative to each other. The system operates by fabricating a first set of conductors on the top surface of a first chip and fabricating a corresponding second set of conductors on the top surface of a second chip. To align the chips, the system electrically charges the first set of conductors and the second set of conductors. The system also places the first chip face-to-face with the second chip, so that the first set of conductors is in close proximity to the second set of conductors. This allows electrostatic forces between the first set of conductors and the second set of conductors to bring the first chip into alignment with the second chip and to hold them in place.

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