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1. 发明授权

US6055235A Switching system 失效
标题翻译：开关系统
公开(公告)号：US6055235A
公开(公告)日：2000-04-25
申请号：US992232
申请日：1997-12-17
申请人： Alain Blanc , Christian Landry , Michel Poret , Jean-Claude Robbe
发明人： Alain Blanc , Christian Landry , Michel Poret , Jean-Claude Robbe
IPC分类号： H04L12/54 , H04L12/70 , H04L12/931 , H04L12/935 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/203 , H04L49/3081 , H04L2012/5625 , H04L2012/563 , H04L2012/5652 , H04L2012/5681
摘要： A cell switching module and switching system for routing cells each having a cell header comprising a plurality of input and output ports; at least one common cell storage connected between the input and output ports and comprising a plurality of storage locations having addresses; a storage section for performing storage of cells coming through any one of the input ports into the common cell storage and comprising a plurality of receiver means for performing the physical interface for the plurality of input ports, a plurality of input routers for connection the input ports to the cell storage, a plurality of ASA registers for providing the input routers with addresses to be used for storing the cells into the cell storage; and a retrieve section for retrieving cells from storage and for transporting them to one of the output ports, where the retrieve section comprises a plurality of output routers for retrieving the data stored in any locations of the cell storage, a plurality of drivers for connecting to the output ports, and a plurality of ARA registers for providing addresses of the cells which are to be outputted from the cell storage to the output routers.
摘要翻译：一种用于路由每个具有包括多个输入和输出端口的小区头的小区的小区切换模块和交换系统; 连接在所述输入和输出端口之间的至少一个公共小区存储器，并且包括具有地址的多个存储位置; 存储部分，用于执行将通过任何一个输入端口的单元存储到公共单元存储器中，并且包括用于执行多个输入端口的物理接口的多个接收器装置;多个输入路由器，用于连接输入端口多个ASA寄存器，用于向所述输入路由器提供用于将所述单元存储到所述单元存储器中的地址; 以及用于从存储器检索单元并将其传送到输出端口之一的检索部分，其中检索部分包括用于检索存储在单元存储器的任何位置的数据的多个输出路由器，多个用于连接到输出端口和多个ARA寄存器，用于提供要从单元存储器输出到输出路由器的单元的地址。

2. 发明授权

US5128666A Protocol and apparatus for a control link between a control unit and several devices 失效
标题翻译：用于控制单元和多个设备之间的控制链路的协议和设备
公开(公告)号：US5128666A
公开(公告)日：1992-07-07
申请号：US573108
申请日：1990-02-20
申请人： Jean-Marie Munier , Michel Poret , Jean-Claude Robbe
发明人： Jean-Marie Munier , Michel Poret , Jean-Claude Robbe
IPC分类号： G06F13/42
CPC分类号： G06F13/423
摘要： An interface and protocol for linking devices (18) with a control unit (10). The interface includes a dedicated request line (30) per device, a dot-ORed acknowledge line (32), at least one clock line (38) transmitting sets of N clock pulses from the control unit to a device during each data exchange, two data line (34, 36) for serial duplex data transmission and a pair of shift registers one being positioned in the control unit and another being positioned in each of the devices. The protocol is such that for either a read or a write operation the control unit issues two request signals in spaced relationship on the request line and the selected device responds with two acknowledge signals is spaced relationship on the acknowledge line with each one of the acknowledge signals falling after the fall of its associated request signal.
摘要翻译：一种用于将设备（18）与控制单元（10）相链接的接口和协议。接口包括每个设备的专用请求线（30），点对应确认线（32），在每个数据交换期间至少一个时钟线（38），其将来自控制单元的N个时钟脉冲的集合发送到设备，两个用于串行双工数据传输的数据线（34,36）和一对移位寄存器，一个位于控制单元中，另一个位于每个设备中。该协议使得对于读取或写入操作，控制单元在请求线上以间隔的关系发出两个请求信号，并且所选择的设备以两个确认信号作出响应，在确认线上与每个确认信号在相关联的请求信号的下降之后下降。

3. 发明授权

US06597656B1 Switch system comprising two switch fabrics 失效
标题翻译：交换机系统包括两个交换结构
公开(公告)号：US06597656B1
公开(公告)日：2003-07-22
申请号：US09317006
申请日：1999-05-24
申请人： Alain Blanc , Sylvie Gohl , Alain Saurel , Bernard Brezzo , Jean-Claude Robbe
发明人： Alain Blanc , Sylvie Gohl , Alain Saurel , Bernard Brezzo , Jean-Claude Robbe
IPC分类号： H04L122
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/309 , H04L49/455 , H04L2012/5627 , H04L2012/5647
摘要： A switching system having at least two switch fabrics. Each fabric has a switch core and a set of SCAL (Switch Core Access Layer) receive and transmit elements. The switch cores are preferably located in the same physical area but the SCALs may be distributed in different physical areas. Port Adapters distributed at different physical areas are connected to the switch fabrics via a particular SCAL element so that each switch core can receive cells from any port adapter and conversely any port adapter may receive data from either switch core. Control logic assigns a particular switch core to one port adapter for normal operations while reserving the other switch core for use when the first core is out of service. Each switch core has a mask mechanism which uses the value in a mask register to alter a bitmap value which controls the routing process. The mask registers in the two switch cores are loaded with complementary values.
摘要翻译：一种具有至少两个交换结构的交换系统。每个结构具有交换机核心和一组SCAL（交换机核心接入层）接收和发送元素。交换机核心优选地位于相同的物理区域中，但是SCAL可以分布在不同的物理区域中。分布在不同物理区域的端口适配器通过特定的SCAL元件连接到交换结构，使得每个交换机核心可以从任何端口适配器接收单元，相反，任何端口适配器可以从交换机核心接收数据。控制逻辑将特定的交换机核心分配给一个端口适配器进行正常操作，同时在第一个核心停止工作时保留另一个交换机内核以供使用。每个交换机核心都有一个掩码机制，使用掩码寄存器中的值来更改控制路由进程的位图值。两个交换机核心中的掩码寄存器加载互补值。

4. 发明授权

US4748587A Device for improving detection of unoperational states in non-attended driven processor 失效
标题翻译：用于改善非参与式驱动处理器中非工作状态检测的装置
公开(公告)号：US4748587A
公开(公告)日：1988-05-31
申请号：US801442
申请日：1985-11-25
申请人： Jacques Combes , Jean-Claude Robbe , Paul Viallon
发明人： Jacques Combes , Jean-Claude Robbe , Paul Viallon
IPC分类号： G06F9/46 , G06F9/48 , G06F11/00 , G06F11/22 , G06F11/30 , G06F11/34
CPC分类号： G06F11/22 , G06F11/0757
摘要： Device for detecting the unoperational states of an interrupt driven processor executing instructions on n priority levels, n-1 being the lowest priority level and 0 the highest priority level. It comprises means (18) for dispatching the unoperational state detection task running on the n-1 priority level at time intervals smaller than a specified time-out delay. A detection timer (1) is set at an initial value each time the task is dispatched and the content is changed stepwise once the task has been dispatched and an interval timer (13) having a minimum step value. Means (20) are responsive to the final value taken by the detection timer when the time-out delay has elapsed, to send a level 0 interrupt to the processor. A REMEMBER LATCH (26) is set at the occurrence of the first next pulse from the interval timer if the detection timer is at its final value and is reset when the level 0 interrupt handling succeeds in restoring the cause of said level 0 interrupt request.
摘要翻译：用于检测执行n个优先级指令的中断驱动处理器的非操作状态的装置，n-1是最低优先级，0是最高优先级。它包括用于以小于指定的超时延迟的时间间隔调度在n-1个优先级上运行的非操作状态检测任务的装置（18）。每当调度任务时，检测定时器（1）被设置为初始值，并且一旦分派了任务并且内容被逐步改变，并且具有最小步长值的间隔定时器（13）。当超时延迟已经过去时，装置（20）响应于检测定时器所采取的最终值，以向处理器发送0级中断。如果检测定时器处于其最终值，则在间隔定时器发生下一个脉冲的情况下设置记忆锁存器（26），并且当电平0中断处理成功恢复所述电平0中断请求的原因时复位。

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