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1. 发明授权

US07382792B2 Queue scheduling mechanism in a data packet transmission system 失效
标题翻译：数据包传输系统中的队列调度机制
公开(公告)号：US07382792B2
公开(公告)日：2008-06-03
申请号：US10065808
申请日：2002-11-21
申请人： Alain Blanc , Bernard Brezzo , Rene Gallezot , Francois Le Mauf , Daniel Wind
发明人： Alain Blanc , Bernard Brezzo , Rene Gallezot , Francois Le Mauf , Daniel Wind
IPC分类号： H04L12/28
CPC分类号： H04L47/6215 , H04L47/2458 , H04L47/28 , H04L47/50 , H04L47/527 , H04L47/6285 , H04W28/14 , H04W72/1242
摘要： A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank, and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides at each packet cycle a value N defining the priority rank to be considered by the queue scheduler whereby a data packet is read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm.
摘要翻译：在数据分组传输系统中的队列调度机制，包括用于发送数据分组的传输设备的数据分组传输系统，用于接收数据分组的接收设备，分别与一组优先级相关联的一组队列设备，每个优先级由用于将由传输设备发送的每个数据分组存储到与其优先级相对应的队列设备中的优先等级，以及队列调度器，用于在每个分组周期读取由普通优先级抢占算法确定的队列中的一个队列中的分组。队列调度机制包括在每个分组周期提供定义要由队列调度器考虑的优先级的值N的信用设备，由队列调度器从对应于优先级N的队列设备读取数据分组，而不是队列设备由普通优先级抢占算法确定。

2. 发明授权

US07061909B2 System and method for controlling the multicast traffic of a data packet switch 失效
公开(公告)号：US07061909B2
公开(公告)日：2006-06-13
申请号：US09950897
申请日：2001-09-10
申请人： Alain Blanc , Bernard Brezzo , Rene Gallezot , Franco Le Maut , Thierry Roman , Daniel Wind
发明人： Alain Blanc , Bernard Brezzo , Rene Gallezot , Franco Le Maut , Thierry Roman , Daniel Wind
IPC分类号： H04L12/56
CPC分类号： H04L49/201 , H04L49/103 , H04L49/3009 , H04L49/3018 , H04L49/3027
摘要： A data switch is provided which routes fixed-size data packets from input ports to output ports, using shared memory which holds a copy of each packet in buffers. Output ports have a queue which contains pointers to buffers holding packets bound for that port. The number of shared memory buffers holding packets is compared to the number of buffer pointers in the output queues. In this way, a Multicast Index (MCI), a metric of the level of multicast traffic, is derived. The switch includes a Switch Core Adaptation Layer (SCAL) which has a multicast input queue. Because traffic is handled based on priority class P, a multicast threshold MCT(P), associated with the multicast input queue, is established per priority. While receiving traffic, the MCI is updated and, for each priority class in each SCAL, the MCI is compared to the MCT(P) to determine whether corresponding multicast traffic must be held.

3. 发明授权

US07385993B2 Queue scheduling mechanism in a data packet transmission system 失效
标题翻译：数据包传输系统中的队列调度机制
公开(公告)号：US07385993B2
公开(公告)日：2008-06-10
申请号：US10065809
申请日：2002-11-21
申请人： Alain Blanc , Rene Gallezot , Francois Le Maut , Daniel Wind
发明人： Alain Blanc , Rene Gallezot , Francois Le Maut , Daniel Wind
IPC分类号： H04L12/56
CPC分类号： H04L47/6215 , H04L47/10 , H04L47/2433 , H04L47/245 , H04L47/39 , H04L47/50 , H04L47/626
摘要： A queue scheduling mechanism in a data packet transmission system, the data packet transmission system including a transmission device for transmitting data packets, a reception device for receiving the data packets, a set of queue devices respectively associated with a set of priorities each defined by a priority rank for storing each data packet transmitted by the transmission device into the queue device corresponding to its priority rank and a queue scheduler for reading, at each packet cycle, a packet in one of the queue devices determined by a normal priority preemption algorithm. The queue scheduling mechanism includes a credit device that provides, at each packet cycle, a value N defining the priority rank to be read by the queue scheduler from the queue device corresponding to the priority N instead of the queue device determined by the normal priority preemption algorithm. The queue scheduling mechanism further includes an exhaustive priority register that registers the value of at least one exhaustive priority rank to be read by the queue scheduler from the queue device corresponding to the exhaustive priority rank rather than from the queue device corresponding to the priority N.
摘要翻译：在数据分组传输系统中的队列调度机制，包括用于发送数据分组的传输设备的数据分组传输系统，用于接收数据分组的接收设备，分别与一组优先级相关联的一组队列设备，每个优先级由用于将由传输设备发送的每个数据分组存储到与其优先级相对应的队列设备中的优先等级，以及队列调度器，用于在每个分组周期读取由普通优先级抢占算法确定的队列中的一个队列中的分组。队列调度机制包括在每个分组周期提供定义队列调度器从对应于优先级N的队列设备中读取的优先等级的值N，而不是由正常优先级抢占确定的队列设备的信用设备算法。队列调度机制还包括一个穷举优先级寄存器，其向与队列调度器读取的至少一个穷举优先等级的值进行比较，该队列设备对应于穷举优先级而不是来自对应于优先级N的队列设备。

4. 发明授权

US07272778B2 Method and systems for improving test of data transmission in multi-channel systems 失效
标题翻译：用于改善多通道系统中数据传输测试的方法和系统
公开(公告)号：US07272778B2
公开(公告)日：2007-09-18
申请号：US10656472
申请日：2003-09-05
申请人： Alain Blanc , Bruno Mesnet , Rene Gallezot
发明人： Alain Blanc , Bruno Mesnet , Rene Gallezot
IPC分类号： H03M13/03
CPC分类号： H04L43/0823 , H04L43/10
摘要： A method and systems to test a communication system (200) comprising a plurality of emitters (205), receivers (210) and channels (220) are disclosed. According to the method of the invention the data used for the test are preprocessed so as to be analyzed on the fly by the receivers during the test. In a preferred embodiment, a connection identifier value characterizing emitter and receiver addresses as well as data properties, if any, is associated to each data and CRC bits are computed to format frames comprising data, connection identifier value and CRC bits (410). During the test, the communication system transmits frames from emitters to corresponding receivers. Upon frames reception, receivers extract data (455), connection identifier value (460) and CRC bits (465) and compute CRC bits on received data (470). The comparison (475) of transmitted and computed CRC bits in receiver allows determining whether or not frames have been well transmitted.
摘要翻译：公开了一种用于测试包括多个发射器（205），接收器（210）和通道（220））的通信系统（200）的方法和系统。根据本发明的方法，用于测试的数据被预处理，以便在测试期间由接收机在飞行中进行分析。在优选实施例中，表征发射器和接收器地址以及数据属性（如果有的话）的连接标识符值与每个数据相关联，并且计算CRC位以格式化包括数据，连接标识符值和CRC位的帧（410）。在测试期间，通信系统将帧从发射器发射到对应的接收机。在帧接收时，接收机提取数据（455），连接标识符值（460）和CRC比特（465），并计算接收数据（470）上的CRC比特。接收机中发送和计算的CRC比特的比较（475）允许确定帧是否被良好地发送。

5. 发明授权

US06606300B1 Flow control process for a switching system and system for performing the same 失效
公开(公告)号：US06606300B1
公开(公告)日：2003-08-12
申请号：US09219081
申请日：1998-12-22
申请人： Alain Blanc , Pierre Debord , Alain Saurel , Bernard Brezzo
发明人： Alain Blanc , Pierre Debord , Alain Saurel , Bernard Brezzo
IPC分类号： H04L1256
CPC分类号： H04L49/3081 , H04L49/1507 , H04L49/201 , H04L49/25 , H04L49/50 , H04L49/506 , H04L2012/563 , H04L2012/5672 , H04Q11/0478
摘要： A flow control process for a switching system having at least one switch core connected through serial communication links to remote and distributed Protocol Adapters or Protocol Engines through Switch Core Access Layer (SCAL) elements. For each input port i, the SCAL element contains a receive Protocol Interface corresponding to the adapter assigned to the input port i and a first serializer for providing attachment to the switch core by means of a first serial communication link. When the cells are received in the switch core, they are deserialized by means of a first deserializer. At each output port, the cells are serialized again by means of a second serializer and then transmitted via a second serial communication link, to the appropriate SCAL. The SCAL contains a second deserializer and a transmit Protocol Interface circuit for permitting attachment of the Protocol Adapter. The flow control process permits two flow control signals, a flow control receive (FCR) from the core to the SCAL, and a flow control transmit (FCX) from the SCAL back to the core. For transmission of the FCR signal in response to the detection of local saturation in the switch core, the process causes transfer of an internal FCR signal to the serializer located within the saturated core. The FCR is introduced in the normal data flow to be conveyed through the second serial link to the remote SCAL corresponding to the saturated input port of the core. An internal control signal can be transmitted to the Protocol Interface that is originating too many cells which results in the overloaded input port of the core. For the transmission of the FCX signal in response to the detection of a saturated Protocol Interface element at one output port, the process generates an internal control signal to the serializer located in the SCAL element. The serializer can introduce a FCX signal in the normal data flow which is conveyed to the core and then decoded by the deserializer in the core. Thus, the core can be informed of the saturation condition that has occurred in the considered output port. Particular adaptations are provided in which the switching system is arranged in a set of individual switching structures mounted in a port expansion mode.

6. 发明授权

US07773602B2 CAM based system and method for re-sequencing data packets 有权
标题翻译：基于CAM的系统和重新排序数据包的方法
公开(公告)号：US07773602B2
公开(公告)日：2010-08-10
申请号：US12123602
申请日：2008-05-20
申请人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
发明人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
IPC分类号： H04L12/28
CPC分类号： H04L67/1002 , H04L47/50 , H04L49/1523 , H04L49/3045 , H04L49/552 , H04L49/9094
摘要： An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.
摘要翻译：该系统的一个实施例在具有至少一个出口适配器的并行分组交换机体系结构中操作，所述出口适配器布置成接收从多个入口适配器发出的数据分组，并且通过多个独立交换平面切换。每个接收到的数据分组属于多个序列中的一个数据分组序列，其中数据分组根据数据分组的至少优先级分配的分组序列号（PSN）进行编号。由至少一个出口适配器接收的每个数据分组具有源标识符，用于标识从其发出的入口适配器。用于恢复接收到的数据分组的序列的系统在出口适配器内操作，并且包括用于在分配的分组缓冲器位置临时存储每个接收的数据分组的缓冲器，控制器和耦合到存储装置和提取装置的确定装置。

7. 发明申请

US20080267206A1 CAM BASED SYSTEM AND METHOD FOR RE-SEQUENCING DATA PACKETS 有权
标题翻译：基于CAM的系统和用于重新排序数据包的方法
公开(公告)号：US20080267206A1
公开(公告)日：2008-10-30
申请号：US12123602
申请日：2008-05-20
申请人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
发明人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
IPC分类号： H04L12/56
CPC分类号： H04L67/1002 , H04L47/50 , H04L49/1523 , H04L49/3045 , H04L49/552 , H04L49/9094
摘要： An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.
摘要翻译：该系统的一个实施例在具有至少一个出口适配器的并行分组交换机体系结构中操作，所述出口适配器布置成接收从多个入口适配器发出的数据分组，并且通过多个独立交换平面切换。每个接收到的数据分组属于多个序列中的一个数据分组序列，其中数据分组根据数据分组的至少优先级分配的分组序列号（PSN）进行编号。由至少一个出口适配器接收的每个数据分组具有源标识符，用于标识从其发出的入口适配器。用于恢复接收到的数据分组的序列的系统在出口适配器内操作，并且包括用于在分配的分组缓冲器位置临时存储每个接收的数据分组的缓冲器，控制器和耦合到存储装置和提取装置的确定装置。

8. 发明授权

US07400629B2 CAM based system and method for re-sequencing data packets 有权
标题翻译：基于CAM的系统和重新排序数据包的方法
公开(公告)号：US07400629B2
公开(公告)日：2008-07-15
申请号：US10723834
申请日：2003-11-26
申请人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
发明人： Alain Blanc , Rene Glaise , Michel Poret , Rene Gallezot
IPC分类号： H04L12/28
CPC分类号： H04L67/1002 , H04L47/50 , H04L49/1523 , H04L49/3045 , H04L49/552 , H04L49/9094
摘要： A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location. Furthermore, controller to extract the packet sequence number, the source identifier and the priority level of each stored data packet. And determination means coupled to the storing means and to the extracting means allow to determine for each sequence of data packet the order of the data packets to be output from the egress adapter.
摘要翻译：公开了一种用于重新排序数据包的系统。在优选实施例中，系统以并行分组交换架构操作，其具有布置成接收从多个入口适配器发出并通过多个独立交换平面切换的数据分组的至少一个出口适配器。每个接收到的数据分组属于多个序列中的一个数据分组序列，其中数据分组根据数据分组的至少优先级分配的分组序列号（PSN）进行编号。由至少一个出口适配器接收的每个数据分组还具有源标识符以识别从其发出的入口适配器。用于恢复接收到的数据分组的序列的系统在出口适配器内操作，并且包括用于在分配的分组缓冲器位置临时存储每个接收到的数据分组的缓冲器。此外，控制器提取每个存储的数据包的包序列号，源标识符和优先级。以及耦合到所述存储装置并且所述提取装置的确定装置允许针对每个数据分组序列确定要从所述出口适配器输出的数据分组的顺序。

9. 发明授权

US06597656B1 Switch system comprising two switch fabrics 失效
标题翻译：交换机系统包括两个交换结构
公开(公告)号：US06597656B1
公开(公告)日：2003-07-22
申请号：US09317006
申请日：1999-05-24
申请人： Alain Blanc , Sylvie Gohl , Alain Saurel , Bernard Brezzo , Jean-Claude Robbe
发明人： Alain Blanc , Sylvie Gohl , Alain Saurel , Bernard Brezzo , Jean-Claude Robbe
IPC分类号： H04L122
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/309 , H04L49/455 , H04L2012/5627 , H04L2012/5647
摘要： A switching system having at least two switch fabrics. Each fabric has a switch core and a set of SCAL (Switch Core Access Layer) receive and transmit elements. The switch cores are preferably located in the same physical area but the SCALs may be distributed in different physical areas. Port Adapters distributed at different physical areas are connected to the switch fabrics via a particular SCAL element so that each switch core can receive cells from any port adapter and conversely any port adapter may receive data from either switch core. Control logic assigns a particular switch core to one port adapter for normal operations while reserving the other switch core for use when the first core is out of service. Each switch core has a mask mechanism which uses the value in a mask register to alter a bitmap value which controls the routing process. The mask registers in the two switch cores are loaded with complementary values.
摘要翻译：一种具有至少两个交换结构的交换系统。每个结构具有交换机核心和一组SCAL（交换机核心接入层）接收和发送元素。交换机核心优选地位于相同的物理区域中，但是SCAL可以分布在不同的物理区域中。分布在不同物理区域的端口适配器通过特定的SCAL元件连接到交换结构，使得每个交换机核心可以从任何端口适配器接收单元，相反，任何端口适配器可以从交换机核心接收数据。控制逻辑将特定的交换机核心分配给一个端口适配器进行正常操作，同时在第一个核心停止工作时保留另一个交换机内核以供使用。每个交换机核心都有一个掩码机制，使用掩码寄存器中的值来更改控制路由进程的位图值。两个交换机核心中的掩码寄存器加载互补值。

10. 发明授权

US6108334A Switching system comprising distributed elements allowing attachment to line adapters 失效
标题翻译：交换系统包括允许连接到线路适配器的分布式元件
公开(公告)号：US6108334A
公开(公告)日：2000-08-22
申请号：US992871
申请日：1997-12-17
申请人： Alain Blanc , Bernard Brezzo , Michel Poret , Alain Saurel
发明人： Alain Blanc , Bernard Brezzo , Michel Poret , Alain Saurel
IPC分类号： H04L12/70 , H04L12/933 , H04L12/935 , H04Q11/04 , H04L12/56
CPC分类号： H04L49/3081 , H04L49/1553 , H04Q11/0478 , H04L2012/5642
摘要： A switching system comprising a switching structure for routing cells from a set of M input ports towards a set of M output ports. The system includes a set of distributed individual Switch Core Access layer elements which communicate with one input and output port of the switching structure by means of a set of serial communication links. Each SCAL element provides attachment to at least one Protocol Adapter and comprises a set of circuits. The receive part of each circuit, which includes at least one first FIFO storage for storing the cells being received, receives the data cells from the attached Protocol Adapter and introduces at least one extra byte to every cell. Each transmit part of the destination circuit, which includes at least one second FIFO storage having a greater capacity than the first FIFO storage, receives all the cells that are generated at the corresponding output port and uses the at least one extra byte for cell buffering. Additionally, each distrubuted SCAL element comprises control means for performing Time Division Multiplexing access of the FIFOs.
摘要翻译：一种交换系统，包括用于将一组M个输入端口的单元路由到一组M个输出端口的交换结构。该系统包括一组分布式的交换机核心接入层元件，它们通过一组串行通信链路与交换结构的一个输入和输出端口通信。每个SCAL元件提供至少一个协议适配器的附件，并且包括一组电路。每个电路的接收部分包括至少一个用于存储接收的单元的第一FIFO存储器，从附加的协议适配器接收数据单元，并向每个单元引入至少一个额外的字节。目的地电路的每个发送部分包括具有比第一FIFO存储器更大的容量的至少一个第二FIFO存储器，接收在相应输出端口处生成的所有单元，并使用该至少一个额外字节用于单元缓冲。另外，每个分散的SCAL元件包括用于执行FIFO的时分多路复用访问的控制装置。

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