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1. 发明授权

US08547148B2 Semiconductor device with dynamically calibrated oscillator 有权
标题翻译：具有动态校准振荡器的半导体器件
公开(公告)号：US08547148B2
公开(公告)日：2013-10-01
申请号：US13026245
申请日：2011-02-12
申请人： Akira Matsumoto , Tatsunori Usugi
发明人： Akira Matsumoto , Tatsunori Usugi
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0995
摘要： A digital compensation phase locked loop circuit of a semiconductor device includes a phase locked loop circuit including a voltage controlled oscillator having capacitors at oscillation nodes and consecutively controlled by an applied voltage, and a digital compensation circuit which variably controls the capacitors at the oscillation nodes of the voltage controlled oscillator in accordance with an input phase difference. A gain of the conventional voltage controlled oscillator whose gain is determined by an applied voltage is discretely changed by a control signal of the digital compensation circuit. The digital compensation circuit dynamically controls the gain so as to secure the optimum phase margin by applying a load (capacitor) to the oscillation node of the voltage controlled oscillator with respect to a phase lead and decreasing the load (capacitor) with respect to a phase delay.
摘要翻译：半导体器件的数字补偿锁相环电路包括：锁相环电路，包括在振荡节点处具有电容器并由施加电压连续控制的压控振荡器;以及数字补偿电路，其可变地控制振荡节点处的电容器压控振荡器根据输入相位差。增益由施加电压决定的传统压控振荡器的增益由数字补偿电路的控制信号离散地改变。数字补偿电路动态地控制增益，以通过相对于相位引线施加负载（电容器）到压控振荡器的振荡节点并相对于相位减小负载（电容器）来确保最佳相位裕度延迟。

2. 发明申请

US20110234274A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110234274A1
公开(公告)日：2011-09-29
申请号：US13026245
申请日：2011-02-12
申请人： Akira MATSUMOTO , Tatsunori Usugi
发明人： Akira MATSUMOTO , Tatsunori Usugi
IPC分类号： H03L7/08
CPC分类号： H03L7/087 , H03L7/0995
摘要： A digital compensation phase locked loop circuit of a semiconductor device includes a phase locked loop circuit including a voltage controlled oscillator having capacitors at oscillation nodes and consecutively controlled by an applied voltage, and a digital compensation circuit which variably controls the capacitors at the oscillation nodes of the voltage controlled oscillator in accordance with an input phase difference. A gain of the conventional voltage controlled oscillator whose gain is determined by an applied voltage is discretely changed by a control signal of the digital compensation circuit. The digital compensation circuit dynamically controls the gain so as to secure the optimum phase margin by applying a load (capacitor) to the oscillation node of the voltage controlled oscillator with respect to a phase lead and decreasing the load (capacitor) with respect to a phase delay.
摘要翻译：半导体器件的数字补偿锁相环电路包括：锁相环电路，包括在振荡节点处具有电容器并由施加电压连续控制的压控振荡器;以及数字补偿电路，其可变地控制振荡节点处的电容器压控振荡器根据输入相位差。增益由施加电压决定的传统压控振荡器的增益由数字补偿电路的控制信号离散地改变。数字补偿电路动态地控制增益，以通过相对于相位引线施加负载（电容器）到压控振荡器的振荡节点并相对于相位减小负载（电容器）来确保最佳相位裕度延迟。

3. 发明申请

US20120188013A1 RECEIVING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：接收电路，包括其的半导体器件和信息处理系统
公开(公告)号：US20120188013A1
公开(公告)日：2012-07-26
申请号：US13349236
申请日：2012-01-12
申请人： Yuji USHIO , Daisuke Hamano , Tatsunori Usugi
发明人： Yuji USHIO , Daisuke Hamano , Tatsunori Usugi
IPC分类号： H03F3/45
CPC分类号： H04L25/0272 , H04L25/0292 , H04L25/03878
摘要： In a receiving circuit, and in a semiconductor device and an information processing system including the receiving circuit, the receiving circuit is configured to amplify a high-speed signal by a greater gain than a low-speed signal with a low electric power consumption. The receiving circuit includes a first amplifier and a second amplifier having a cutoff frequency lower than a cutoff frequency of the first amplifier. A received signal is inputted to the first amplifier and the second amplifier, an output from the second amplifier is subtracted from an output from the first amplifier, and a result is outputted from the receiving circuit.
摘要翻译：在接收电路中，并且在包括接收电路的半导体器件和信息处理系统中，接收电路被配置为以比具有低功耗的低速信号更大的增益来放大高速信号。接收电路包括第一放大器和具有低于第一放大器的截止频率的截止频率的第二放大器。接收信号被输入到第一放大器和第二放大器，从第一放大器的输出中减去来自第二放大器的输出，并且从接收电路输出结果。

4. 发明申请

US20120187986A1 LATCH CIRCUIT, CDR CIRCUIT, AND RECEIVER 审中-公开
标题翻译：锁存电路，CDR电路和接收器
公开(公告)号：US20120187986A1
公开(公告)日：2012-07-26
申请号：US13349195
申请日：2012-01-12
申请人： Daisuke Hamano , Tatsunori Usugi
发明人： Daisuke Hamano , Tatsunori Usugi
IPC分类号： H03L7/06 , H03K3/356
CPC分类号： H03K3/356139 , H03L7/0807 , H04L7/033
摘要： A receiving circuit that consumes less electric power is provided. The present invention provides a latch circuit that latches a differential signal by interrupting an electric current generated by a differential input using a corresponding differential output when the differential signal is differentially amplified. By using the latch circuit, transmitted data can be received even if the voltage difference of the differential signal components of the received signal is small. As a result, the number of amplifiers can be reduced, thereby enabling the power consumption of the receiver to be reduced.
摘要翻译：提供消耗较少电力的接收电路。本发明提供了一种锁存电路，其通过在差分信号被差分放大时中断使用相应的差分输出的由差分输入产生的电流来锁存差分信号。通过使用锁存电路，即使接收信号的差分信号分量的电压差小，也可以接收发送数据。结果，可以减少放大器的数量，从而能够降低接收机的功耗。

5. 发明授权

US07369069B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07369069B2
公开(公告)日：2008-05-06
申请号：US11482071
申请日：2006-07-07
申请人： Tatsunori Usugi , Kazuhisa Suzuki , Masatoshi Tsuge
发明人： Tatsunori Usugi , Kazuhisa Suzuki , Masatoshi Tsuge
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G06F1/24
摘要： A semiconductor device including a clock signal generation circuit and a plurality of circuit blocks operating in synchronization with the clock signal, in which each of the plurality of the circuit blocks conducts resetting treatment receiving the interruption signal reset_in outputted in synchronization with the clock signal in the course of frequency acquisition, whereby the timing margin is improved greatly to facilitate the design of timing for a case of conducting interruption between a plurality of circuit blocks operating at high speed simultaneously and decrease circuit scale and power consumption.
摘要翻译：一种半导体器件，包括时钟信号产生电路和与时钟信号同步操作的多个电路块，其中多个电路块中的每个电路块进行与在时钟信号中同步输出的中断信号reset_in的复位处理频率采集的过程，从而大大提高了定时裕度，以便于同时设计高速运行的多个电路块之间导通中断的情况的定时，并降低电路规模和功耗。

6. 发明授权

US08456205B2 Phase-frequency comparator and serial transmission device 失效
标题翻译：相位比较器和串行传输装置
公开(公告)号：US08456205B2
公开(公告)日：2013-06-04
申请号：US12987108
申请日：2011-01-08
申请人： Tatsunori Usugi , Takeshi Isezaki , Takeshi Koyama
发明人： Tatsunori Usugi , Takeshi Isezaki , Takeshi Koyama
IPC分类号： H03L7/06
CPC分类号： H03D13/004
摘要： Disclosed is a phase-frequency comparator stabilizing a loop band width by a simple circuit, there is provided a phase-frequency comparator which is a phase-frequency comparator of inputting a reference clock and a feedback clock and outputting an up signal to a frequency synthesizer and a down signal to the frequency synthesizer, which is provided with a first phase-frequency comparing circuit, a second phase comparing circuit, and a delay circuit portion inputting the reference clock and the feedback clock and providing a predetermined relative delay to an input of the first phase-frequency comparing circuit and an input of the second phase comparing circuit, in which frequency comparison is carried out by the first phase-frequency comparing circuit, and phase comparison is carried out by the first phase-frequency comparing circuit and the second phase comparing circuit controlling a latch.
摘要翻译：公开了一种通过简单的电路来稳定环路带宽的相位 - 频率比较器，提供了一个相位 - 频率比较器，它是输入参考时钟和反馈时钟的相位 - 频率比较器，并向上升频率合成器以及向频率合成器提供的向下信号，其提供有第一相位频率比较电路，第二相位比较电路和输入参考时钟和反馈时钟的延迟电路部分，并向第一相位频率比较电路和第二相位比较电路的输入，其中由第一相位频率比较电路执行频率比较，并且相位比较由第一相位频率比较电路和第二相位比较电路相位比较电路控制锁存器。

7. 发明申请

US20070040715A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20070040715A1
公开(公告)日：2007-02-22
申请号：US11482071
申请日：2006-07-07
申请人： Tatsunori Usugi , Kazuhisa Suzuki , Masatoshi Tsuge
发明人： Tatsunori Usugi , Kazuhisa Suzuki , Masatoshi Tsuge
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G06F1/24
摘要： A semiconductor device including a clock signal generation circuit and a plurality of circuit blocks operating in synchronization with the clock signal, in which each of the plurality of the circuit blocks conducts resetting treatment receiving the interruption signal reset_in outputted in synchronization with the clock signal in the course of frequency acquisition, whereby the timing margin is improved greatly to facilitate the design of timing for a case of conducting interruption between a plurality of circuit blocks operating at high speed simultaneously and decrease circuit scale and power consumption.
摘要翻译：一种半导体器件，包括时钟信号产生电路和与时钟信号同步操作的多个电路块，其中多个电路块中的每个电路块进行与在时钟信号中同步输出的中断信号reset_in的复位处理频率采集的过程，从而大大提高了定时裕度，以便于同时设计高速运行的多个电路块之间导通中断的情况的定时，并降低电路规模和功耗。

8. 发明授权

US08625730B2 Phase locked loop, CDR circuit, and receiving circuit 失效
标题翻译：锁相环，CDR电路和接收电路
公开(公告)号：US08625730B2
公开(公告)日：2014-01-07
申请号：US13180620
申请日：2011-07-12
申请人： Tatsunori Usugi , Daisuke Hamano
发明人： Tatsunori Usugi , Daisuke Hamano
IPC分类号： H03D3/24
CPC分类号： H03L7/235 , H03L7/087
摘要： In a phase locked loop, frequency-divided clocks each of which is given a phase difference of at least one cycle of a feedback clock are inputted to a first phase comparator and a second phase comparator, respectively, which are made to perform phase comparison with a reference clock. Then, outputs of the first and second phase comparators are weighted by a result of the phase comparison of a receive signal and the feedback clock, and phase adjustment of the feedback clock is phase adjusted using the weighted outputs. Thereby, it is possible to lower a frequency of the reference clock and consequently to suppress power consumption.
摘要翻译：在锁相环中，分别给予反馈时钟的至少一个周期的相位差的分频时钟分别被输入到与第一相位比较器和第二相位比较器进行相位比较，参考时钟。然后，通过接收信号和反馈时钟的相位比较的结果对第一和第二相位比较器的输出进行加权，并且使用加权输出对反馈时钟的相位调整进行相位调整。由此，能够降低基准时钟的频率，能够抑制功耗。

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