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1. 发明授权

US09741434B2 Resistance change memory 有权
公开(公告)号：US09741434B2
公开(公告)日：2017-08-22
申请号：US14018287
申请日：2013-09-04
申请人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
发明人： Akira Katayama , Masahiro Takahashi , Tsuneo Inaba , Hyuck Sang Yim , Dong Keun Kim , Byoung Chan Oh , Ji Wang Lee
IPC分类号： G11C5/06 , G11C13/00 , G11C11/16
CPC分类号： G11C13/004 , G11C5/06 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2013/0054
摘要： According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.

2. 发明授权

US08947920B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08947920B2
公开(公告)日：2015-02-03
申请号：US14018148
申请日：2013-09-04
申请人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
发明人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1659
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, unit structures and a reference signal generator. Each structure includes a first end, a first transistor, a first local line, a variable resistance element, a second transistor, a second local line, and a third transistor coupled in series. The reference signal generator includes first to fourth global lines, and first and second ones of the unit structures. The first unit structure is coupled at the first end to the first global line and coupled at the second end to the third global line. The second unit structure is coupled at the first end to the fourth global line and coupled at the second end to the second global line.
摘要翻译：根据一个实施例，存储器件包括存储器单元，读出放大器，单元结构和参考信号发生器。每个结构包括第一端，第一晶体管，第一局部线，可变电阻元件，第二晶体管，第二本地线和串联耦合的第三晶体管。参考信号发生器包括第一至第四全局线，以及第一和第二单元结构。第一单元结构在第一端耦合到第一全局线并且在第二端耦合到第三全局线。第二单元结构在第一端耦合到第四全局线并且在第二端耦合到第二全局线。

3. 发明授权

US09263114B2 Electronic device 有权
标题翻译：电子设备
公开(公告)号：US09263114B2
公开(公告)日：2016-02-16
申请号：US14563690
申请日：2014-12-08
申请人： Ji-Wang Lee , Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Ji-Wang Lee , Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00 , G11C11/15 , G11C11/56
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/5607 , G11C11/5657 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/28 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
摘要翻译：半导体存储单元包括根据存储在其中的值具有不同电阻值的第一至第N可变电阻元件，其中N是等于或大于2的自然数; 具有第一参考电阻值的参考电阻元件; 以及分别对应于第一至第N可变电阻元件的第一至第N比较单元，并且每个比较单元确定相应的可变电阻元件的电阻值是否大于或小于第二参考电阻值，其中第一至第N 比较单元通常耦合到参考电阻元件。

4. 发明授权

US09177641B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US09177641B2
公开(公告)日：2015-11-03
申请号：US14018306
申请日：2013-09-04
申请人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
发明人： Masahiro Takahashi , Tsuneo Inaba , Dong Keun Kim , Ji Wang Lee
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C13/004 , G11C11/1673 , G11C2013/0054 , G11C2213/79
摘要： According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
摘要翻译：根据一个实施例，存储器件包括存储单元，读出放大器和电阻器。读出放大器包括第一输入和第二输入，根据第一和第二输入之间的差输出信号，并且在第二输入端选择性地耦合到存储单元。电阻器位于读出放大器的第一输入端和接地节点之间的第一路径中。

5. 发明授权

US09535834B2 Electronic device including memory arrays with variable resistance storage elements arranged on different sides of a word line driving unit 有权
标题翻译：电子设备包括具有布置在字线驱动单元的不同侧上的可变电阻存储元件的存储器阵列
公开(公告)号：US09535834B2
公开(公告)日：2017-01-03
申请号：US14563645
申请日：2014-12-08
申请人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G06F12/08 , G11C13/00 , G11C11/4099 , G11C11/16
CPC分类号： G11C13/004 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F12/0207 , G06F12/08 , G06F12/0875 , G06F2212/2024 , G06F2212/452 , G06F2212/60 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/4099 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C2013/0054 , G11C2213/79 , G11C2213/82
摘要： An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.
摘要翻译：电子设备包括半导体器件，其中半导体器件包括：用于驱动多个字线的字线驱动单元; 布置在字线驱动单元的一侧的第一单元阵列; 布置在所述字线驱动单元的另一侧的第二单元阵列; 布置在所述第一单元阵列和所述第二单元阵列之间的偏置电压产生单元，用于基于流过所述第一单元阵列中包括的所述第一参考电阻元件的电流和所述第二单元中包括的所述第二参考电阻元件来产生偏置电压阵列第一读取控制单元; 和第二读取控制单元。

6. 发明授权

US09183951B2 Resistance change memory and test method of the same 有权
标题翻译：电阻变化记忆和测试方法相同
公开(公告)号：US09183951B2
公开(公告)日：2015-11-10
申请号：US14201534
申请日：2014-03-07
申请人： Tsuneo Inaba , Dong Keun Kim
发明人： Tsuneo Inaba , Dong Keun Kim
IPC分类号： G11C13/00 , G11C29/12 , G11C8/08 , G11C29/06 , G11C29/50 , G11C11/16
CPC分类号： G11C29/12005 , G11C8/08 , G11C11/16 , G11C11/1675 , G11C13/0004 , G11C13/0069 , G11C29/06 , G11C29/50008 , G11C2013/009 , G11C2029/1202
摘要： According to one embodiment, a resistance change memory includes a memory cell array, an address counter, a word line driver, a power supply circuit, and a write driver. Memory cells include resistive storage elements and cell transistors. The power supply circuit generates a stress voltage different from a power supply voltage used to write data into the memory cells in a normal operation. The write driver applies the stress voltage across first bit and source lines to pass a stress current through the memory cell selected by a first word line. The write driver applies the stress voltage across second bit and source lines to pass the stress current through the memory cell selected by a second word line.
摘要翻译：根据一个实施例，电阻变化存储器包括存储单元阵列，地址计数器，字线驱动器，电源电路和写入驱动器。存储单元包括电阻存储元件和单元晶体管。电源电路产生与用于在正常操作中将数据写入存储单元的电源电压不同的应力电压。写驱动器将应力电压施加在第一位和源极线之间以将应力电流传递通过由第一字线选择的存储单元。写驱动器将应力电压施加在第二位和源极线之间，以使应力电流通过由第二字线选择的存储单元。

7. 发明授权

US08274826B2 NAND type flash memory 有权
标题翻译： NAND型闪存
公开(公告)号：US08274826B2
公开(公告)日：2012-09-25
申请号：US12838867
申请日：2010-07-19
申请人： Toshifumi Hashimoto , Noboru Shibata , Toshiki Hisada , Tsuneo Inaba
发明人： Toshifumi Hashimoto , Noboru Shibata , Toshiki Hisada , Tsuneo Inaba
IPC分类号： G11C16/04
CPC分类号： G11C16/06
摘要： According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block.
摘要翻译：根据一个实施例，NAND型闪速存储器包括设置在第一和第二存储器平面之间的第一传输晶体管，第一传输晶体管的第一电位传输端共同连接到第一NAND块中的第一字线，第二字配置在第三NAND块中的第二转移晶体管，设置在第一存储器平面的第一端的第二转移晶体管，第二转移晶体管的第一电位转移端连接到第二NAND块中的第三字线，以及第三转移晶体管设置在第二存储器平面的第二端，第三传输晶体管的第一电位传输端连接到第四NAND块中的第四字线。

8. 发明授权

US08120948B2 Data writing method for magnetoresistive effect element and magnetic memory 有权
标题翻译：磁阻效应元件和磁存储器的数据写入方法
公开(公告)号：US08120948B2
公开(公告)日：2012-02-21
申请号：US12561495
申请日：2009-09-17
申请人： Masahiko Nakayama , Hisanori Aikawa , Tsuneo Inaba , Kenji Tsuchida , Sumio Ikegawa , Hiroaki Yoda , Naoharu Shimomura
发明人： Masahiko Nakayama , Hisanori Aikawa , Tsuneo Inaba , Kenji Tsuchida , Sumio Ikegawa , Hiroaki Yoda , Naoharu Shimomura
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1675
摘要： A data writing method for a magnetoresistive effect element of an aspect of the present invention including generating a write current in which a falling period from the start of a falling edge to the end of the falling edge is longer than a rising period from the start of a rising edge to the end of the rising edge, and flowing the write current through the magnetoresistive effect element which comprises a first magnetic layer having an invariable magnetizing direction, a second magnetic layer having a variable magnetizing direction, and a tunnel barrier layer provided between the first magnetic layer and the second magnetic layer, to change the magnetizing direction of the second magnetic layer.
摘要翻译：一种用于本发明一个方面的磁阻效应元件的数据写入方法，包括产生写入电流，其中从下降沿开始到下降沿结束的下降周期长于从开始上升沿到上升沿结束，并且使写入电流流过磁阻效应元件，该磁阻效应元件包括具有不变磁化方向的第一磁性层，具有可变磁化方向的第二磁性层和设置在可变磁化方向之间的隧道势垒层，第一磁性层和第二磁性层，以改变第二磁性层的磁化方向。

9. 发明申请

US20100237321A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100237321A1
公开(公告)日：2010-09-23
申请号：US12793172
申请日：2010-06-03
申请人： Tsuneo Inaba
发明人： Tsuneo Inaba
IPC分类号： H01L27/24 , H01L27/11
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/1659 , G11C13/0004 , G11C13/0023 , G11C2213/79 , H01L27/24
摘要： A semiconductor memory device includes the first transistor having first and second source/drain diffusion regions positioned below a second bit line to sandwich the first word line therebetween, and the second source/drain diffusion region positioned between the first and second word lines and connected to a first bit line, a second transistor having second and third source/drain diffusion regions positioned below the second bit line to sandwich the second word line therebetween, a first resistive memory element formed below the second bit line above the first source/drain diffusion region, and having terminals connected to the second bit line and the first source/drain diffusion region, and a second resistive memory element formed below the second bit line above the third source/drain diffusion region, and having terminals connected to the second bit line and the third source/drain diffusion region.
摘要翻译：半导体存储器件包括第一晶体管，其具有位于第二位线下方的第一和第二源极/漏极扩散区，以将第一字线夹在其间，第二源/漏扩散区位于第一和第二字线之间并连接到第一位线，具有位于第二位线下方以将第二字线夹在其间的第二和第三源极/漏极扩散区的第二晶体管，形成在第一源极/漏极扩散区域之上的第二位线下方的第一电阻性存储元件并且具有连接到第二位线和第一源极/漏极扩散区域的端子，以及形成在第三源极/漏极扩散区域之上的第二位线下方的第二电阻性存储元件，并且具有连接到第二位线的端子和第三源极/漏极扩散区域。

10. 发明申请

US20100232224A1 NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非挥发性半导体存储器件
公开(公告)号：US20100232224A1
公开(公告)日：2010-09-16
申请号：US12721001
申请日：2010-03-10
申请人： Takashi MAEDA , Tsuneo Inaba
发明人： Takashi MAEDA , Tsuneo Inaba
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C16/0483 , H01L27/11573 , H01L27/11578 , H01L27/11582
摘要： A memory cell array has plural memory strings arranged therein, each of which including a plurality of electrically-rewritable memory transistors and selection transistors. Each memory string includes a body semiconductor layer including four or more columnar portions, and a joining portion formed to join the lower ends thereof. An electric charge storage layer is formed to surround a side surface of the columnar portions. A first conductive layer is formed to surround a side surface of the columnar portions as well as the electric charge storage layer. A plurality of second conductive layers are formed on side surfaces of the joining portion via an insulation film, and function as control electrodes of a plurality of back-gate transistors formed at a respective one of the joining portions.
摘要翻译：存储单元阵列具有布置在其中的多个存储器串，每个存储单元包括多个电可重写存储晶体管和选择晶体管。每个存储器串包括包括四个或更多个柱状部分的主体半导体层和形成为连接其下端的接合部分。形成电荷存储层以包围柱状部分的侧表面。形成第一导电层以包围柱状部分的侧表面以及电荷存储层。多个第二导电层经由绝缘膜形成在接合部分的侧表面上，并且用作形成在相应一个接合部分的多个后栅极晶体管的控制电极。

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