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1. 发明申请

US20180286483A1 PROGRAMMING MEMORY DEVICES 审中-公开
公开(公告)号：US20180286483A1
公开(公告)日：2018-10-04
申请号：US15477048
申请日：2017-04-01
申请人： Akira Goda , Tommaso Vali , Carmine Miccoli , Pranav Kalavade
发明人： Akira Goda , Tommaso Vali , Carmine Miccoli , Pranav Kalavade
IPC分类号： G11C16/04 , G11C16/34 , G11C16/12 , G11C8/08
CPC分类号： G11C16/0483 , G11C8/08 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/3459 , G11C2211/5621
摘要： Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.

2. 发明授权

US10217515B2 Programming memory devices 有权
公开(公告)号：US10217515B2
公开(公告)日：2019-02-26
申请号：US15477048
申请日：2017-04-01
申请人： Akira Goda , Tommaso Vali , Carmine Miccoli , Pranav Kalavade
发明人： Akira Goda , Tommaso Vali , Carmine Miccoli , Pranav Kalavade
IPC分类号： G11C16/04 , G11C16/34 , G11C16/12 , G11C8/08
摘要： Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.

3. 发明授权

US08681562B2 Memories and methods of programming memories 有权
标题翻译：记忆和程序记忆的方法
公开(公告)号：US08681562B2
公开(公告)日：2014-03-25
申请号：US13051599
申请日：2011-03-18
申请人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
发明人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C16/3459
摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
摘要翻译：公开了用于调整存储器上部页面编程的装置和方法。在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

4. 发明申请

US20120176843A1 MEMORIES AND METHODS OF PROGRAMMING MEMORIES 有权
标题翻译：记忆和编程记忆的方法
公开(公告)号：US20120176843A1
公开(公告)日：2012-07-12
申请号：US13051599
申请日：2011-03-18
申请人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
发明人： Pranav Kalavade , Akira Goda , Tommaso Vali , Violante Moschiano
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C16/3459
摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.
摘要翻译：公开了用于调整存储器上部页面编程的装置和方法。在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

5. 发明授权

US10102903B1 Write process for a non volatile memory device 有权
公开(公告)号：US10102903B1
公开(公告)日：2018-10-16
申请号：US15476654
申请日：2017-03-31
申请人： Tommaso Vali , Violante Moschiano , Andrea D'Alessandro , Pranav Kalavade
发明人： Tommaso Vali , Violante Moschiano , Andrea D'Alessandro , Pranav Kalavade
IPC分类号： G11C11/34 , G11C11/56 , G11C16/10 , G11C16/34
摘要： An apparatus is described. The apparatus includes a non volatile memory device that includes a controller to implement a coarse write process for the non volatile memory device. The non volatile memory device includes storage cells to store more than two logic states, wherein, the coarse write process is to perform a verify operation early in the coarse write process to identify less responsive storage cells and provide additional charge to the less responsive storage cells as compared to non less responsive storage cells that are to be programmed to a same logical state as the less responsive storage cells without performing a following verify operation after each pulse of charge applied during the coarse write process.

6. 发明申请

US20130272071A1 DETERMINING SOFT DATA FOR COMBINATIONS OF MEMORY CELLS 有权
标题翻译：确定记忆细胞组合的软数据
公开(公告)号：US20130272071A1
公开(公告)日：2013-10-17
申请号：US13444443
申请日：2012-04-11
申请人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
发明人： Violante Moschiano , Tommaso Vali , Mark A. Hawes
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells including a first and a second memory cell each programmable to one of a number of program states, wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states, and a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program states of the first and second memory cells.
摘要翻译：本公开包括用于确定存储器单元的组合的软数据的装置和方法。多个实施例包括存储单元的阵列，其包括第一和第二存储单元，每个第一和第二存储器单元可编程为多个程序状态之一，其中第一和第二存储器单元的编程状态的组合对应于多个数据状态，以及耦合到阵列并被配置为确定与第一和第二存储器单元的程序状态相关联的软数据的缓冲器和/或控制器以及与对应于程序状态的组合的数据状态相关联的软数据至少部分地基于与第一和第二存储器单元的程序状态相关联的软数据。

7. 发明授权

US08395939B2 Compensation of back pattern effect in a memory device 有权
标题翻译：在存储器件中补偿背面图案效果
公开(公告)号：US08395939B2
公开(公告)日：2013-03-12
申请号：US13090754
申请日：2011-04-20
申请人： Tommaso Vali , Violante Moschiano , Giovanni Santin
发明人： Tommaso Vali , Violante Moschiano , Giovanni Santin
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/26 , G11C29/76 , G11C29/789 , G11C29/82 , G11C2211/5621 , G11C2211/5642
摘要： In one or more of the disclosed embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
摘要翻译：在所公开的一个或多个实施例中，读取操作被补偿以用于背面图案效果。通过偏置字线的读取操作产生位线电流。作为背景图案效果测量阶段的一部分，在预定的时间间隔，将位线的放电状态的指示存储在耦合到每个位线的一组N个锁存器的锁存器中。在测量阶段结束时，锁存器组包含一个多位字，它是该特定串行存储单元所经历的反向图案效应的指示。这种背面图案效果指示用于随后的读取操作以调整操作的时间。

8. 发明授权

US08233329B2 Architecture and method for memory programming 有权
标题翻译：内存编程的架构和方法
公开(公告)号：US08233329B2
公开(公告)日：2012-07-31
申请号：US12365589
申请日：2009-02-04
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati , Violante Moschiano
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C27/02 , G11C2211/5642 , G11C2211/5646
摘要： Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
摘要翻译：例如，公开了存储器，存储器件和系统的编程方法。在一种这样的方法中，根据是否禁止与数据线相邻的一条或多条数据线，要编程的存储器的每条数据线被不同地偏置。在一个这样的系统中，连接电路将对应于目标数据线的禁止状态的数据提供给与与目标数据线相邻的数据线相关联的寻呼缓冲器。

9. 发明申请

US20100122016A1 DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY 有权
标题翻译：动态SLC / MLC块分配非易失性存储器
公开(公告)号：US20100122016A1
公开(公告)日：2010-05-13
申请号：US12269766
申请日：2008-11-12
申请人： Giulio Marotta , Luca De Santis , Tommaso Vali
发明人： Giulio Marotta , Luca De Santis , Tommaso Vali
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/16 , G06F12/0246 , G06F2212/7202 , G11C2211/5641
摘要： Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.
摘要翻译：公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。当内存使用量低时，使用SLC模式。当内存使用率高时，使用MLC模式。动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。

10. 发明授权

US07394699B2 Sense amplifier for a non-volatile memory device 有权
标题翻译：用于非易失性存储器件的感应放大器
公开(公告)号：US07394699B2
公开(公告)日：2008-07-01
申请号：US11651687
申请日：2007-01-10
申请人： Tommaso Vali , Giovanni Santin , Michele Incarnati
发明人： Tommaso Vali , Giovanni Santin , Michele Incarnati
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： The memory device has a plurality of memory cells each coupled to a bitline. A feedback transistor is coupled to the bitline and provides voltage feedback on the bitline's precharge status. A biasing transistor is coupled to the feedback transistor. The biasing transistor provides a bias voltage to the feedback transistor in response to a reference voltage on the biasing transistor. A cascode-connected transistor is coupled to the feedback transistor and the biasing transistor. This transistor provides a stable bias voltage to the biasing transistor. An output latch circuit is coupled to the bitline for providing a latched output of the memory cell's data.
摘要翻译：存储器件具有多个存储单元，每个存储器单元都耦合到位线。反馈晶体管耦合到位线，并对位线的预充电状态提供电压反馈。偏置晶体管耦合到反馈晶体管。偏置晶体管响应于偏置晶体管上的参考电压向反馈晶体管提供偏置电压。共源共栅连接的晶体管耦合到反馈晶体管和偏置晶体管。该晶体管向偏置晶体管提供稳定的偏置电压。输出锁存电路耦合到位线以提供存储器单元数据的锁存输出。

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