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1. 发明授权

US4954855A Thin film transistor formed on insulating substrate 失效
标题翻译：绝缘基板上形成薄膜晶体管
公开(公告)号：US4954855A
公开(公告)日：1990-09-04
申请号：US113360
申请日：1987-10-28
申请人： Akio Mimura , Yoshikazu Hosokawa , Takaya Suzuki , Takashi Aoyama , Nobutake Konishi , Yutaka Misawa , Kenji Miyata
发明人： Akio Mimura , Yoshikazu Hosokawa , Takaya Suzuki , Takashi Aoyama , Nobutake Konishi , Yutaka Misawa , Kenji Miyata
IPC分类号： H01L21/336 , H01L29/45 , H01L29/49 , H01L29/786
CPC分类号： H01L29/66757 , H01L29/456 , H01L29/458 , H01L29/4908 , H01L29/7866 , H01L29/78675
摘要： A thin film transistor formed on an insulating sulstrate is disclosed in which metal silicide layers are formed in a thin film made of a monocrystalline, polycrystalline, or amorphous semiconductor material, to be used as source and drain regions, and further a gate electrode includes a metal silicide layer.
摘要翻译：公开了一种形成在绝缘硅片上的薄膜晶体管，其中金属硅化物层形成在由单晶，多晶或非晶半导体材料制成的薄膜中，用作源极和漏极区域，并且还包括一个栅电极金属硅化物层。

2. 发明授权

US4746961A Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US4746961A
公开(公告)日：1988-05-24
申请号：US59785
申请日：1987-06-08
申请人： Nobutake Konishi , Kenji Miyata , Yoshikazu Hosokawa , Takaya Suzuki , Akio Mimura
发明人： Nobutake Konishi , Kenji Miyata , Yoshikazu Hosokawa , Takaya Suzuki , Akio Mimura
IPC分类号： H01L27/12 , G02F1/1368 , H01L29/08 , H01L29/78 , H01L29/786 , H01L29/161 , H01L29/12
CPC分类号： G02F1/1368 , H01L29/0847 , H01L29/78621 , H01L2029/7863
摘要： This invention relates to the structure of a field effect transistor, which is suitable for liquid crystal display of an active matrix scheme and there is disclosed a new structure for the field effect transistor, in which at least one of the source region and the drain region is of multi-layered structure, in which high impurity concentration portions and low impurity concentration portions are alternately superposed on each other.
摘要翻译：本发明涉及适用于有源矩阵方案的液晶显示的场效应晶体管的结构，并且公开了一种用于场效应晶体管的新结构，其中源区和漏区中的至少一个是多层结构，其中高杂质浓度部分和低杂质浓度部分彼此交替重叠。

3. 发明授权

US4942441A Thin film semiconductor device and method of manufacturing the same 失效
标题翻译：薄膜半导体器件及其制造方法
公开(公告)号：US4942441A
公开(公告)日：1990-07-17
申请号：US30623
申请日：1987-03-27
申请人： Nobutake Konishi , Yoshikazu Hosokawa , Akio Mimura , Takaya Suzuki , Jun-ichi Ohwada , Hideaki Kawakami , Kenji Miyata
发明人： Nobutake Konishi , Yoshikazu Hosokawa , Akio Mimura , Takaya Suzuki , Jun-ichi Ohwada , Hideaki Kawakami , Kenji Miyata
IPC分类号： G02F1/1368 , H01L21/336 , H01L21/77 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1214 , G02F1/1368 , H01L21/84 , H01L29/7839 , G02F2202/103 , G02F2202/104
摘要： Complementary thin fillm transistors (C-TFT) formed on an insulating substrate, comprising a pair of highly resistive n-type silicon islands, a pair of heavily doped n-type regions formed in one of the islands to form source and drain regions of n-channel TFT, a pair of contacts formed on the surface of the other island and establishing a high potential barrier when the underlying region is of n-type and a low potential barrier when the underlying region is inverted to be of p-type. The process for manufacturing complementary TFTs can be simplified significantly.
摘要翻译：形成在绝缘衬底上的互补薄填充晶体管（C-TFT），包括一对高电阻性n型硅岛，在一个岛中形成的一对重掺杂n型区，以形成n和沟道TFT，一对触点形成在另一个岛的表面上，并且当下面的区域为n型时建立高电势势垒，并且当下面的区域被反相为p型时形成低电势势垒。制造互补TFT的工艺可以大大简化。

4. 发明授权

US5153702A Thin film semiconductor device and method for fabricating the same 失效
标题翻译：薄膜半导体器件及其制造方法
公开(公告)号：US5153702A
公开(公告)日：1992-10-06
申请号：US203935
申请日：1988-06-08
申请人： Takashi Aoyama , Nobutake Konishi , Takaya Suzuki , Kenji Miyata , Saburo Oikawa , Yoshiaki Okajima , Genshiro Kawachi , Eimi Adachi
发明人： Takashi Aoyama , Nobutake Konishi , Takaya Suzuki , Kenji Miyata , Saburo Oikawa , Yoshiaki Okajima , Genshiro Kawachi , Eimi Adachi
IPC分类号： G02F1/1368 , H01L21/20 , H01L21/336 , H01L29/04 , H01L29/786
CPC分类号： H01L29/66757 , H01L21/2022 , H01L27/1229 , H01L29/045 , H01L29/78675 , G02F1/1368 , G02F2202/104
摘要： This invention relates to a thin film semiconductor device and a method for fabricating it, and more particularly a thin film semiconductor device suitably applicable to a display device in an active matrix system and a method for fabricating it. In this invention, the structure of a thin film semiconductor device for improving the characteristic thereof and particularly the structure relative to the dominant orientation of a poly-Si film as an active layer of a thin film transistor (TFT) is disclosed. A method for fabricating a thin film semiconductor device which is capable of forming a poly-Si film at a relatively low process temperature is disclosed. Further, a display device in an active matrix system which provided high performance and high image quality is disclosed. The poly-Si film having a dominant orientation of (111) is formed by forming a poly-Si film on the semiconductor substrate at a temperature up to 570.degree. C. and annealing the substrate at a temperature up to 640.degree. C.
摘要翻译：本发明涉及一种薄膜半导体器件及其制造方法，更具体地说，涉及适用于有源矩阵系统中的显示装置的薄膜半导体器件及其制造方法。在本发明中，公开了用于改善其特性的薄膜半导体器件的结构，特别是关于作为薄膜晶体管（TFT）的有源层的多晶硅膜的主导方向的结构。公开了一种能够在较低处理温度下形成多晶硅薄膜的薄膜半导体器件的制造方法。此外，公开了提供高性能和高图像质量的有源矩阵系统中的显示装置。通过在半导体衬底上在高达570℃的温度下形成多晶硅膜，并在高达640℃的温度下对衬底进行退火，形成具有（111）主导取向性的多晶硅膜。

5. 发明授权

US4943837A Thin film semiconductor device and method of fabricating the same 失效
标题翻译：薄膜半导体器件及其制造方法
公开(公告)号：US4943837A
公开(公告)日：1990-07-24
申请号：US166518
申请日：1988-03-10
申请人： Nobutake Konishi , Kikuo Ono , Takaya Suzuki , Kenji Miyata
发明人： Nobutake Konishi , Kikuo Ono , Takaya Suzuki , Kenji Miyata
IPC分类号： H01L21/205 , H01L21/336 , H01L27/12 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/42384 , H01L29/78666 , Y10S438/958
摘要： A thin film transistor and a method of fabricating the transistor are disclosed. The gate electrode of this thin film transistor is made small in thickness so that active hydrogen for hydrogenating passivation can penetrate in a surface layer of channel region having substantially uniform thickness, through the gate electrode. Thus, hydrogenation can be effectively carried out for the thin film transistor, independently of the length of a channel formed in the transistor.
摘要翻译：公开了一种薄膜晶体管及其制造方法。该薄膜晶体管的栅电极的厚度较小，因此用于氢化钝化的活性氢可通过栅电极穿透具有基本均匀厚度的沟道区的表面层。因此，可以独立于在晶体管中形成的沟道的长度，有效地对薄膜晶体管进行氢化。

6. 发明授权

US4173674A Dielectric insulator separated substrate for semiconductor integrated circuits 失效
标题翻译：用于半导体集成电路的绝缘体绝缘体分离衬底
公开(公告)号：US4173674A
公开(公告)日：1979-11-06
申请号：US888981
申请日：1978-03-22
申请人： Akio Mimura , Takaya Suzuki , Seturo Yagiyu
发明人： Akio Mimura , Takaya Suzuki , Seturo Yagiyu
IPC分类号： H01L21/762 , B32B7/00 , B32B9/04 , H01L21/304 , H01L21/316
CPC分类号： H01L21/76297 , Y10T428/265
摘要： A dielectric insulator separated substrate comprises a plurality of monocrystalline semiconductor island regions in which circuit elements are to be formed and a support region for supporting the island regions while a dielectric film formed on the supporting region electrically separates the island regions from each other. The supporting region comprises crystalline semiconductor layers and at least one oxygen diffusion preventive film laminated alternately.The extreme outer polycrystalline semiconductor layer of the supporting region is polished to such a thickness as to prevent the substrate from being curved greatly by the wedge action due to the oxygen diffusion. Since the extreme outer polycrystalline semiconductor layer thus polished has a flat surface, the handling of the substrate is easy. The substrate devoid of any curveness deformation assures a highly accurate formation of the circuit elements in the island regions.
摘要翻译：介质绝缘体分离衬底包括要形成电路元件的多个单晶半导体岛区域和用于支撑岛区的支撑区域，同时形成在支撑区域上的电介质膜将岛区彼此电分离。支撑区域包括结晶半导体层和交替层压的至少一个氧扩散防止膜。支撑区域的极外部多晶半导体层被抛光到这样的厚度，以防止由于氧扩散而产生的楔形作用使衬底大大弯曲。由于这样抛光的极外部多晶半导体层具有平坦的表面，所以基板的处理容易。没有任何弯曲变形的基板确保岛状区域中的电路元件的高精度地形成。

7. 发明授权

US4079506A Method of preparing a dielectric-isolated substrate for semiconductor integrated circuitries 失效
标题翻译：制备用于半导体集成电路的电介质隔离衬底的方法
公开(公告)号：US4079506A
公开(公告)日：1978-03-21
申请号：US637959
申请日：1975-12-05
申请人： Takaya Suzuki , Seturoo Yagyuu , Akio Mimura
发明人： Takaya Suzuki , Seturoo Yagyuu , Akio Mimura
IPC分类号： H01L21/3205 , H01L21/762 , H01L23/52 , H01L21/304 , H01L21/316
CPC分类号： H01L21/76297 , Y10S148/043 , Y10S148/051 , Y10S148/085 , Y10S148/097 , Y10S148/122 , Y10S148/15
摘要： In the preparation of a dielectric-isolated substrate for semiconductor integrated circuits which comprises a plurality of silicon single crystalline islands in which circuit elements are formed, a region made of an alternate laminate of silicon polycrystalline layers and silicon oxide films for supporting the plurality of silicon single crystalline islands, and a silicon oxide film interposed between the silicon single crystalline islands and the support region for isolating each of the silicon single crystalline islands from the remaining ones and the support region, the formation of three to twelve silicon polycrystalline layers in the support region can remarkably reduce the bending of the substrate resulting from the growth stress of the silicon polycrystalline layers or from the difference in thermal expansion coefficients between the single crystalline silicon and the polycrystalline silicon, and therefore produces a dielectric-isolated substrate showing little bending.
摘要翻译：在制备用于半导体集成电路的绝缘隔离衬底的制备中，该衬底包括形成电路元件的多个单晶硅岛，由用于支撑多个硅的多晶硅层和氧化硅膜的交替叠层制成的区域单晶岛和置于硅单结晶岛和支撑区之间的氧化硅膜，用于隔离其中的每一个单晶岛和支撑区，在载体中形成三至十二个硅多晶层区域可以显着降低由硅多晶层的生长应力产生的衬底的弯曲或者由单晶硅和多晶硅之间的热膨胀系数的差异，因此产生几乎没有弯曲的介电隔离衬底。

8. 发明授权

US4017341A Method of manufacturing semiconductor integrated circuit with prevention of substrate warpage 失效
标题翻译：制造半导体集成电路的方法，防止基板翘曲
公开(公告)号：US4017341A
公开(公告)日：1977-04-12
申请号：US604947
申请日：1975-08-15
申请人： Takaya Suzuki , Akio Mimura , Seturo Yagyu , Shinji Okuhara
发明人： Takaya Suzuki , Akio Mimura , Seturo Yagyu , Shinji Okuhara
IPC分类号： H01L21/20 , H01L21/223 , H01L21/762 , H01L21/764 , H01L21/76
CPC分类号： H01L21/76264 , H01L21/2007 , H01L21/223 , H01L21/764 , H01L21/76275 , H01L21/76289 , Y10S148/003 , Y10S148/085 , Y10S148/118 , Y10S148/122
摘要： In a monolithic semiconductor integrated circuit, when polycrystalline semiconductor is used in a portion of substrate insulatively supporting plural semiconductor single crystal regions forming circuit elements, the oxidation process of the impurity diffusion process at high temperatures and in oxygen atmosphere is started after a passivation film such as silicon oxide or silicon nitride, to prevent oxygen from diffusing or penetrating into the surface of the polycrystalline semiconductor, has been formed on the same surface. By leaving the passivation film lying on that surface during the oxidation and diffusion process warping of the substrate that may be caused due to the diffusion or penetration of oxygen into the polycrystalline semiconductor region is prevented.
摘要翻译：在单片半导体集成电路中，当多个半导体用于绝缘地支撑形成电路元件的多个半导体单晶区域的基板的一部分中时，在钝化膜之后开始高温和氧气氛中的杂质扩散处理的氧化处理作为氧化硅或氮化硅，以防止氧扩散或渗透到多晶半导体的表面中，已经形成在同一表面上。通过在氧化和扩散过程中使钝化膜位于该表面上，防止由于氧进入多晶半导体区域而扩散或渗透而引起的基板翘曲。

9. 发明授权

US4388342A Method for chemical vapor deposition 失效
标题翻译：化学气相沉积方法
公开(公告)号：US4388342A
公开(公告)日：1983-06-14
申请号：US154025
申请日：1980-05-28
申请人： Takaya Suzuki , Yosuke Inoue , Takashi Aoyama
发明人： Takaya Suzuki , Yosuke Inoue , Takashi Aoyama
IPC分类号： C30B25/16 , C23C16/455 , C23C16/52 , H01L21/205 , H01L21/31 , B05D5/12
CPC分类号： H01L21/02532 , C23C16/455 , C23C16/52 , H01L21/02381 , H01L21/02576 , H01L21/02579 , H01L21/0262 , Y10T436/12
摘要： A method of forming by CVD technique a layer of material with good uniformity and reproducibility on the surfaces of a plurality of substrates supported within the reaction chamber. The feature of the invention is that a gaseous mixture containing a reaction gas is supplied into the reaction chamber from the inlet of the reaction chamber and the auxiliary gas nozzle provided between the inlet and the exhaust in a predetermined control manner. Moreover, part of the gaseous mixture within the reaction chamber is sampled from the gas flow for the measurement of the concentration of the reaction gas, and from the measured results is determined the rate of gas supply from the auxiliary gas nozzle.
摘要翻译：通过CVD技术在支撑在反应室内的多个基板的表面上形成具有良好均匀性和再现性的材料层的方法。本发明的特征是含有反应气体的气体混合物以预定的控制方式从反应室的入口和设置在入口和排气口之间的辅助气体喷嘴供入反应室。此外，反应室内的气体混合物的一部分从气流中取样以测量反应气体的浓度，并且从测量结果确定来自辅助气体喷嘴的气体供应速率。

10. 发明授权

US4164436A Process for preparation of semiconductor devices utilizing a two-step polycrystalline deposition technique to form a diffusion source 失效
标题翻译：使用两步多晶沉积技术制备半导体器件以形成扩散源的方法
公开(公告)号：US4164436A
公开(公告)日：1979-08-14
申请号：US925792
申请日：1978-07-18
申请人： Mitsuru Ura , Kenji Miyata , Takaya Suzuki , Takuzo Ogawa
发明人： Mitsuru Ura , Kenji Miyata , Takaya Suzuki , Takuzo Ogawa
IPC分类号： H01L21/22 , H01L21/205 , H01L21/225 , H01L29/04 , H01L29/08 , H01L29/866
CPC分类号： H01L29/866 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/2257 , H01L29/04 , H01L29/0834 , Y10S148/122 , Y10S438/983
摘要： A semiconductor substrate having a single crystal semiconductor layer of one conductivity type exposed to the surface thereof is maintained at a temperature lower than the temperature at which the semiconductors is precipitated from the gas phase. In this state, a gas of a starting material of a semiconductor, a gas containing impurities capable of forming a semiconductor of the other conductivity type and a carrier gas therefore are fed onto the semiconductor substrate. Then, the semiconductor substrate is heated to form an amorphous or polycrystalline semiconductor layer of the other conductivity type on the semiconductor substrate. Simultaneously, the impurities of the other conductivity type are diffused from the amorphous or polycrystal semiconductor layer into the substrate which has a single crystal semiconductor layer of one conductivity type, to form a single crystal semiconductor layer having a p-n junction just below the amorphous or polycrystal semiconductor layer between the amorphous or polycrystalline semiconductor layer and the single crystal semiconductor layer of one conductivity type.In a p-n junction to be formed according to this process, the distribution of the concentration of impurities can be controlled precisely, and the step-like distribution of the concentration of impurities can be attained very well.
摘要翻译：具有暴露于其表面的一种导电类型的单晶半导体层的半导体衬底保持在比从气相中半导体析出的温度低的温度。在这种状态下，半导体衬底上的半导体原料气体，含能够形成其它导电类型的半导体的气体和载气的气体被馈送到半导体衬底上。然后，半导体衬底被加热以在半导体衬底上形成另一导电类型的非晶或多晶半导体层。同时，其他导电类型的杂质从非晶或多晶半导体层扩散到具有一种导电类型的单晶半导体层的衬底中，以形成具有刚好在无定形或多晶的下面的pn结的单晶半导体层非晶或多晶半导体层与一种导电类型的单晶半导体层之间的半导体层。

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