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1. 发明授权

US08745275B2 Blade server apparatus 有权
标题翻译：刀片服务器设备
公开(公告)号：US08745275B2
公开(公告)日：2014-06-03
申请号：US13209994
申请日：2011-08-15
申请人： Akio Ikeya , Takashi Aoyagi , Kenji Kashiwagi , Naohiro Sezaki , Kazunori Nakajima
发明人： Akio Ikeya , Takashi Aoyagi , Kenji Kashiwagi , Naohiro Sezaki , Kazunori Nakajima
IPC分类号： G06F3/00
CPC分类号： G06F15/7803
摘要： A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the SMP virtual connecting unit is provided within the firmware.
摘要翻译：一种刀片服务器装置，包括多个服务器模块，用于在其上安装多个服务器模块的背板以及具有连接到多个服务器模块的SMP的布线的SMP耦合装置。每个服务器模块具有由固件控制的一个或多个处理器和用于管理其自己的服务器模块的模块管理器，模块管理器具有用于向每个处理器通知处理器ID的ID确定器，每个处理器具有处理单元和SMP虚拟连接单元，用于指示要发送从处理单元接收到的分组的SMP耦合设备的布线，以及用于将处理器ID转换并通知给SMP虚拟连接单元的ID转换器设置在固件内。

2. 发明申请

US20120054469A1 BLADE SERVER APPARATUS 有权
标题翻译：刀片服务器设备
公开(公告)号：US20120054469A1
公开(公告)日：2012-03-01
申请号：US13209994
申请日：2011-08-15
申请人： AKIO IKEYA , Takashi Aoyagi , Kenji Kashiwagi , Naohiro Sezaki , Kazunori Nakajima
发明人： AKIO IKEYA , Takashi Aoyagi , Kenji Kashiwagi , Naohiro Sezaki , Kazunori Nakajima
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F15/7803
摘要： A blade server apparatus including a plurality of server modules, a backplane for mounting the plurality of server modules thereon, and an SMP coupling device having wiring lines to SMP couple the plurality of server modules. Each of the server modules has one or more processors controlled by firmware and a module manager for managing its own server module, the module manager has an ID determiner for informing each processor of a processor ID, each processor has a processing unit and an SMP virtual connecting unit for instructing ones of wiring lines of the SMP coupling device through which a packet received from the processing unit is to be transmitted, and an ID converter for converting the processor ID and informing it to the virtual connecting unit is provided within the firmware.
摘要翻译：一种刀片服务器装置，包括多个服务器模块，用于在其上安装多个服务器模块的背板以及具有连接到多个服务器模块的SMP的布线的SMP耦合装置。每个服务器模块具有由固件控制的一个或多个处理器和用于管理其自己的服务器模块的模块管理器，模块管理器具有用于向每个处理器通知处理器ID的ID确定器，每个处理器具有处理单元和SMP虚拟连接单元，用于指示要从所述处理单元接收到的分组的所述SMP耦合设备的布线的哪个布线，以及用于将所述处理器ID转换并通知所述虚拟连接单元的ID转换器设置在所述固件内。

3. 发明授权

US06573170B2 Process for multilayer wiring connections and bonding pad adhesion to dielectric in a semiconductor integrated circuit device 有权
标题翻译：在半导体集成电路器件中的多层布线连接和焊盘粘附到电介质的工艺
公开(公告)号：US06573170B2
公开(公告)日：2003-06-03
申请号：US09748163
申请日：2000-12-27
申请人： Takashi Aoyagi , Atsushi Ogishima , Hirotaka Kobayashi , Yuji Hara
发明人： Takashi Aoyagi , Atsushi Ogishima , Hirotaka Kobayashi , Yuji Hara
IPC分类号： H01L2100
CPC分类号： H01L23/53223 , H01L21/32051 , H01L21/76802 , H01L21/76807 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L27/10882 , H01L27/10894 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05006 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05187 , H01L2224/05624 , H01L2224/05644 , H01L2224/13099 , H01L2224/131 , H01L2224/13144 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4847 , H01L2224/48475 , H01L2224/48624 , H01L2224/48644 , H01L2224/48699 , H01L2224/48724 , H01L2224/48744 , H01L2224/48844 , H01L2224/85051 , H01L2224/85205 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/00 , H01L2224/48824
摘要： A semiconductor integrated circuit device including a plurality of holes in an interlayer insulating film beneath a bonding pad wherein a plug is buried in the respective holes and is made of the same conductive film (W/TiN/Ti) as a plug in a through-hole. Any wire as a second layer is not formed in a lower region of the bonding pad. The plug buried in the holes is connected only to the upper boding pad and is not connected to a lower wire.
摘要翻译：一种半导体集成电路器件，包括在接合焊盘下方的层间绝缘膜中的多个孔，其中，插塞被埋在相应的孔中，并且由相同的导电膜（W / TiN / Ti）制成，孔。作为第二层的任何线都不形成在接合焊盘的下部区域中。埋在孔中的插头仅连接到上焊盘，并且不连接到下导线。

4. 发明授权

US06815761B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06815761B2
公开(公告)日：2004-11-09
申请号：US10419944
申请日：2003-04-22
申请人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
发明人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/115
摘要： In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

5. 发明授权

US06583467B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06583467B2
公开(公告)日：2003-06-24
申请号：US10179217
申请日：2002-06-26
申请人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
发明人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/115
摘要： In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
摘要翻译：在半导体集成电路装置中，在形成有条状元件分离区域5的基板上形成有AND型闪速存储器，并且夹持在元件分离区域5之间的有源区域L形成为条状。使用含有氮或碳的硅单晶衬底作为半导体衬底，以减少错位缺陷和接头泄漏，从而提高可靠性和产率。

6. 发明授权

US06444514B1 Semiconductor integrated circuit device and manufacturing method thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06444514B1
公开(公告)日：2002-09-03
申请号：US09677758
申请日：2000-10-03
申请人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
发明人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/115
摘要： In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
摘要翻译：在半导体集成电路装置中，在形成有条状元件分离区域5的基板上形成有AND型闪速存储器，并且夹持在元件分离区域5之间的有源区域L形成为条状。使用含有氮或碳的硅单晶衬底作为半导体衬底，以减少错位缺陷和结漏电，从而提高可靠性和产率。

7. 发明授权

US08352665B2 Computer system and bus assignment method 有权
标题翻译：计算机系统和总线分配方法
公开(公告)号：US08352665B2
公开(公告)日：2013-01-08
申请号：US12486927
申请日：2009-06-18
申请人： Keishi Nakayama , Keitaro Uehara , Takashi Aoyagi , Shinichiro Toya
发明人： Keishi Nakayama , Keitaro Uehara , Takashi Aoyagi , Shinichiro Toya
IPC分类号： G06F13/20 , G06F3/00 , G06F13/36 , G06F13/00
CPC分类号： G06F13/4022
摘要： To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.
摘要翻译：为了能够接管分配给逻辑分区的IO配置，重新分配逻辑分区，并使IO访问正常工作。计算机系统具有服务器，其具有IO桥，交换机具有用于通过总线与服务器的IO桥连接的第一IO桥，以及用于通过总线连接到多个IO设备的多个第二IO桥，以及总线号分配用于将相互不同的PCI总线号固定地分配给多个第二IO桥的管理装置。

8. 发明申请

US20120159241A1 INFORMATION PROCESSING SYSTEM 审中-公开
标题翻译：信息处理系统
公开(公告)号：US20120159241A1
公开(公告)日：2012-06-21
申请号：US13327190
申请日：2011-12-15
申请人： MOTOI NISHIJIMA , Takashi Nishiyama , Takashi Aoyagi
发明人： MOTOI NISHIJIMA , Takashi Nishiyama , Takashi Aoyagi
IPC分类号： G06F11/20 , G06F13/40
CPC分类号： G06F11/2043 , G06F11/1417 , G06F11/1423 , G06F11/2035
摘要： An information processing system may not degrade a processor, if the system is designed so as to satisfy connection restrictions between processors and chipsets. In the system a route switching function is provided to control the connection between a CPU and a BIOS ROM among a plurality of CPUs and the BIOS ROM. When a fault occurs in a particular CPU, a route connecting the BIOS ROM and another CPU in which a fault does not occur is determined, and then the route switching is performed on the basis of the determined route information.
摘要翻译：如果系统被设计为满足处理器和芯片组之间的连接限制，则信息处理系统可能不会降低处理器。在系统中，提供路由切换功能，以控制多个CPU和BIOS ROM之间的CPU和BIOS ROM之间的连接。当在特定CPU中发生故障时，确定连接BIOS ROM和不发生故障的另一CPU的路由，然后基于确定的路由信息进行路由切换。

9. 发明申请

US20100036995A1 COMPUTER SYSTEM AND BUS ASSIGNMENT METHOD 有权
标题翻译：计算机系统和总线分配方法
公开(公告)号：US20100036995A1
公开(公告)日：2010-02-11
申请号：US12486927
申请日：2009-06-18
申请人： Keishi Nakayama , Keitaro Uehara , Takashi Aoyagi , Shinichiro Toya
发明人： Keishi Nakayama , Keitaro Uehara , Takashi Aoyagi , Shinichiro Toya
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： To make it possible to take over an IO configuration that is assigned to logical partitions in reallocation of the logical partitions, and to make an IO access work normally. A computer system has a server having an IO bridge, a switch that has a first IO bridge for connecting with the IO bridge of the server through a bus and plural second IO bridges for connecting to plural IO devices through a bus, and bus number assignment management means for fixedly assigning mutually different PCI bus numbers to the plural second IO bridges.
摘要翻译：为了能够接管分配给逻辑分区的IO配置，重新分配逻辑分区，并使IO访问正常工作。计算机系统具有服务器，其具有IO桥，交换机具有用于通过总线与服务器的IO桥连接的第一IO桥，以及用于通过总线连接到多个IO设备的多个第二IO桥，以及总线号分配用于将相互不同的PCI总线号固定地分配给多个第二IO桥的管理装置。

10. 发明授权

US5616880A Keyboard musical instrument equipped with hammer shank stopper where hammer assembly rebounds without deflection of shank 失效
标题翻译：键盘乐器配有锤柄止动器，其中锤组件反弹而无偏转柄
公开(公告)号：US5616880A
公开(公告)日：1997-04-01
申请号：US519424
申请日：1995-08-25
申请人： Hajime Hayashida , Takashi Aoyagi , Satoshi Inoue , Ringi Nozue , Kiyoshi Kawamura , Shigeaki Sato
发明人： Hajime Hayashida , Takashi Aoyagi , Satoshi Inoue , Ringi Nozue , Kiyoshi Kawamura , Shigeaki Sato
IPC分类号： G10C3/16 , G10C5/00 , G10D15/00 , G10F1/22 , G10H1/34
CPC分类号： G10C5/005
摘要： An acoustic upright piano, an electronic sound system and a hammer stopper form in combination a keyboard musical instrument for generating acoustic sounds in an acoustic sound mode and electronic sounds in an electronic sound mode, and the hammer stopper has a rotatable shaft extending in a lower space under damper blocks of damper assemblies, cushion members projecting into an upper space over the damper blocks and connecting brackets provided between the rotatable shaft and the cushion members, thereby perfectly interrupting hammer motions before an impact on strings in the electronic sound mode.
摘要翻译：声立式钢琴，电子声音系统和锤子止动器组合起来以键盘乐器形成声音模式中的声音和电子声音模式的电子声音，并且音锤止动器具有在下部延伸的可旋转轴阻尼器组件的阻尼器块下方的空间，缓冲构件突出到阻尼器块上方的上部空间和设置在可旋转轴和缓冲构件之间的连接托架，从而在电子声音模式下对琴弦的撞击之前完全中断琴锤运动。

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