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    • 1. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME
    • 半导体集成电路装置及其制造方法
    • US20090243658A1
    • 2009-10-01
    • US12350681
    • 2009-01-08
    • Akinori YOKOIShigeru Nakahara
    • Akinori YOKOIShigeru Nakahara
    • H03K19/0944H01L29/68H01L21/336H01L29/78
    • H01L27/0629H01L27/0805
    • A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance. At this point in time, a resistance value as desired is attained through combination of decoupling capacitors having threshold voltages Vth differing from each other.
    • 在高技术的情况下需要使用由具有增强的静电击穿电阻的交叉耦合去耦电容器表示的去耦电容器,由于IR降低而导致电源线上AC噪声降低的电路。 还提供了用于抑制由于共振而导致的电源线上的交流噪声的电路。 构成具有增强的静电击穿电阻的交叉耦合去耦电容器的MOS晶体管具有较低的阈值电压Vth,从而减小每个MOS晶体管的源极和漏极之间的电阻,导致IR降低。 此外,阻尼电阻对于抑制电源线上的AC噪声是有效的,并且每个MOS晶体管的源极到漏极电阻被用作阻尼电阻。 在这个时间点,通过组合具有彼此不同的阈值电压Vth的去耦电容来获得希望的电阻值。
    • 2. 发明授权
    • Semiconductor integrated circuit device and method for manufacturing the same
    • 半导体集成电路器件及其制造方法
    • US07719310B2
    • 2010-05-18
    • US12350681
    • 2009-01-08
    • Akinori YokoiShigeru Nakahara
    • Akinori YokoiShigeru Nakahara
    • H03K19/003
    • H01L27/0629H01L27/0805
    • A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance. At this point in time, a resistance value as desired is attained through combination of decoupling capacitors having threshold voltages Vth differing from each other.
    • 在高技术的情况下需要使用由具有增强的静电击穿电阻的交叉耦合去耦电容器表示的去耦电容器,由于IR降低而导致电源线上AC噪声降低的电路。 还提供了用于抑制由于共振而导致的电源线上的交流噪声的电路。 构成具有增强的静电击穿电阻的交叉耦合去耦电容器的MOS晶体管具有较低的阈值电压Vth,从而减小每个MOS晶体管的源极和漏极之间的电阻,导致IR降低。 此外,阻尼电阻对于抑制电源线上的AC噪声是有效的,并且每个MOS晶体管的源极到漏极电阻被用作阻尼电阻。 在这个时间点,通过组合具有彼此不同的阈值电压Vth的去耦电容来获得希望的电阻值。
    • 3. 发明申请
    • Semiconductor memory device
    • 半导体存储器件
    • US20050013160A1
    • 2005-01-20
    • US10917321
    • 2004-08-13
    • Keiichi HigetaShigeru NakaharaHiroaki Nambu
    • Keiichi HigetaShigeru NakaharaHiroaki Nambu
    • G11C8/02G11C11/41G11C11/412G11C11/413G11C11/417H01L21/8244H01L27/10H01L27/11G11C11/00
    • G11C11/417G11C11/412
    • Disclosed herein is a semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.
    • 这里公开了一种半导体存储器件,其具有包括CMOS触发器电路型存储单元的存储器阵列,其能够提高噪声容限,使得读取速度快并降低功耗。 在半导体存储器件中,将存储单元的工作电压设定得高于外围电路的工作电压。 构成存储单元的MOS晶体管的阈值电压被设定为高于构成外围电路的MOS晶体管的阈值电压。 构成存储单元的MOS晶体管的栅极绝缘膜形成为当被转换为相同材料的绝缘膜时,构成构成外围电路的MOS晶体管的栅极绝缘膜更厚。 此外,字线选择电平和位线预充电电平被设置为与外围电路的工作电压的电平相同。
    • 4. 发明申请
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US20050013159A1
    • 2005-01-20
    • US10917320
    • 2004-08-13
    • Satoshi IwahashiShigeru NakaharaTakeshi SuzukiKeiichi Higeta
    • Satoshi IwahashiShigeru NakaharaTakeshi SuzukiKeiichi Higeta
    • G11C11/419G11C7/10G11C8/16G11C11/41G11C11/417G11C11/00
    • G11C7/1069G11C7/1051G11C8/16G11C11/4125
    • The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.
    • 本发明提供了一种新型的半导体集成电路装置,其具有存储电路,高速存储器和大容量存储电路,能够加速和促进定时设定。 半导体集成电路器件设有第一放大电路; 其包括第一导电类型的第一MOSFET,其具有为存储单元分别连接的多个位线提供的栅极,并且分别在提供给位线的预充电电压下分别保持在截止状态,作为读取电路 存储器单元根据选择字线和存储器信息的操作确定存储器电流是否流动; 并且分别与用于位线的选择信号相关联地进入操作状态,并且还设置有第二放大器电路,其包括: 多个第二导电类型的第二MOSFET,其分别具有分别被提供有第一放大器电路的多个放大信号并且以并联配置连接的栅极; 并且其形成对应于第一放大器电路的放大信号的放大信号。
    • 8. 发明授权
    • Semiconductor integrated circuit device for scan testing
    • 半导体集成电路器件进行扫描测试
    • US08086889B2
    • 2011-12-27
    • US12256535
    • 2008-10-23
    • Yuichi ItoYasuhiro FujimuraKoki TsutsumidaShigeru Nakahara
    • Yuichi ItoYasuhiro FujimuraKoki TsutsumidaShigeru Nakahara
    • G06F1/04G01R31/28
    • G01R31/318552
    • A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.
    • 扫描链组结构,其中为LSI中的每个时钟树系统形成的一组扫描链进行重新连接处理,使得扫描链组不存在于通过对由时钟提供的 一个系统的时钟树的区域,并且分配区域中的连接距离变短;测试时钟输入机构,其中要输入到分配区域的测试时钟是独立的子时钟相位;以及开/关机构 实现要输入到分配区域的时钟。 此外,同时执行的扫描/扫描测试在一个区域或单个区域之间被限制,并且在所有区域中以及在所有区域之间的测试通过多次测试步骤来执行。
    • 10. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    • 半导体集成电路设备
    • US20090113230A1
    • 2009-04-30
    • US12256535
    • 2008-10-23
    • Yuichi ItoYasuhiro FujimuraKoki TsutsumidaShigeru Nakahara
    • Yuichi ItoYasuhiro FujimuraKoki TsutsumidaShigeru Nakahara
    • G01R31/3183G06F11/263G06F1/10H01L21/8232
    • G01R31/318552
    • A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.
    • 扫描链组结构,其中为LSI中的每个时钟树系统形成的一组扫描链进行重新连接处理,使得扫描链组不存在于通过对由时钟提供的 一个系统的时钟树的区域,并且分配区域中的连接距离变短;测试时钟输入机构,其中要输入到分配区域的测试时钟是独立的子时钟相位;以及开/关机构 实现要输入到分配区域的时钟。 此外,同时执行的扫描/扫描测试在一个区域或单个区域之间被限制,并且通过多次测试步骤在所有区域和所有区域之间进行测试。