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1. 发明授权

US5576518A Via-structure of a multilayer interconnection ceramic substrate 失效
标题翻译：多层互连陶瓷衬底的通孔结构
公开(公告)号：US5576518A
公开(公告)日：1996-11-19
申请号：US439945
申请日：1995-05-12
申请人： Akinobu Shibuya , Mitsuru Kimura
发明人： Akinobu Shibuya , Mitsuru Kimura
IPC分类号： H05K3/46 , H01L21/48 , H01L23/498 , H01L23/538 , H05K1/02
CPC分类号： H01L23/5384 , H01L21/485 , H01L23/49827 , H01L2924/0002 , H01L2924/09701
摘要： A via-structure off a multilayer interconnection ceramic substrate for a multi-chip module, a semiconductor package and an insulating substrate has a high strength and a high reliability being produced at a low cost. A gap is provided at an interface between a via-conductor and ceramics, and filled with a resin. The resin is preferably of a thermosetting polyimide resin or a benzo-cyclo-butene resin.
摘要翻译：用于多芯片模块，半导体封装和绝缘衬底的多层互连陶瓷衬底的通孔结构具有高成本的高强度和高可靠性。在通孔导体和陶瓷之间的界面处提供间隙，并填充树脂。树脂优选为热固性聚酰亚胺树脂或苯并环丁烯树脂。

2. 发明授权

US5485352A Element joining pad for semiconductor device mounting board 失效
标题翻译：用于半导体器件安装板的元件接合焊盘
公开(公告)号：US5485352A
公开(公告)日：1996-01-16
申请号：US358196
申请日：1994-12-16
申请人： Akinobu Shibuya , Mitsuru Kimura
发明人： Akinobu Shibuya , Mitsuru Kimura
IPC分类号： H01L23/12 , H01L23/498 , H05K3/24 , H05K1/09
CPC分类号： H05K3/246 , H01L23/49811 , H01L23/49866 , H01L2924/0002 , H01L2924/09701 , H05K1/092
摘要： An element joining pad for a semiconductor device mounting board includes a thick-film metalized layer, a barrier layer, and a Ni plating layer. The thick-film metalized layer is selectively formed on a low-temperature sintered board and consists of one of a metal and an alloy which can be sintered at 500.degree. C. or more and 1,200.degree. C. or less. The barrier layer is formed on the thick-film metalized layer and constituted by one of a Rh plating layer and a Ru plating layer. The Ni plating layer is formed on the barrier layer.
摘要翻译：用于半导体器件安装板的元件接合焊盘包括厚膜金属化层，阻挡层和Ni镀覆层。厚膜金属化层选择性地形成在低温烧结板上，由金属和合金之一组成，可以在500℃以上1200℃以下烧结。阻挡层形成在厚膜金属化层上，由Rh镀层和Ru镀层之一构成。在阻挡层上形成Ni镀层。

3. 发明授权

US08531023B2 Substrate for semiconductor package and method of manufacturing thereof 有权
标题翻译：半导体封装用基板及其制造方法
公开(公告)号：US08531023B2
公开(公告)日：2013-09-10
申请号：US13383895
申请日：2010-06-25
申请人： Akinobu Shibuya , Akira Ouchi
发明人： Akinobu Shibuya , Akira Ouchi
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/563 , H01L23/3121 , H01L23/3128 , H01L23/3157 , H01L23/498 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01004 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H05K1/0218 , H05K1/0242 , H05K1/0243 , H05K2201/09736 , H05K2201/09845 , H05K2201/10674 , H01L2924/00
摘要： Disclosed is a substrate for a semiconductor package in which leakage of radiation noise from a gap between a semiconductor element and a mounting substrate can be prevented. The substrate for the semiconductor package includes a coplanar waveguide including a signal and ground electrodes on the mounting substrate, the signal electrode flip-chip connected to the semiconductor element, the ground electrodes arranged on both sides of the signal electrode with intervals therebetween. A step part is formed in the ground electrodes in an outer circumferential part of a mounting region of the semiconductor element, the step part having a larger distance between upper surfaces of the mounting substrate and the ground electrode in the outer circumferential part of the mounting region than such distance in the mounting region, and an insulator for covering the signal electrode in the outer circumferential part of the mounting region is formed.
摘要翻译：公开了一种用于半导体封装的衬底，其中可以防止辐射噪声从半导体元件和安装衬底之间的间隙泄漏。用于半导体封装的衬底包括共面波导，其包括安装衬底上的信号和接地电极，连接到半导体元件的信号电极倒装芯片，布置在信号电极的两侧上的接地电极，间隔。在半导体元件的安装区域的外周部的接地电极中形成台阶部，台阶部在安装基板的上表面与安装区域的外周部的接地电极之间具有较大的距离形成安装区域的距离，并且形成用于覆盖安装区域的外周部分中的信号电极的绝缘体。

4. 发明授权

US06818469B2 Thin film capacitor, method for manufacturing the same and printed circuit board incorporating the same 失效
标题翻译：薄膜电容器及其制造方法以及包含该薄膜电容器的印刷电路板
公开(公告)号：US06818469B2
公开(公告)日：2004-11-16
申请号：US10445330
申请日：2003-05-27
申请人： Toru Mori , Akinobu Shibuya , Shintaro Yamamichi
发明人： Toru Mori , Akinobu Shibuya , Shintaro Yamamichi
IPC分类号： H01L2100
CPC分类号： H05K1/162 , H01L2224/04105 , H01L2224/32225 , H01L2224/73267 , H05K1/185 , H05K3/429 , H05K2201/0317 , H05K2201/09509
摘要： A thin film capacitor is provided with a substrate having a thickness equal to or more than 2 &mgr;m and equal to or less than 100 &mgr;m; a lower electrode on the substrate, which includes at least a highly elastic electrode and an anti-oxidation electrode on the highly elastic electrode; a dielectric thin film on the first lower electrode; and an upper electrode on the dielectric thin film; wherein the highly elastic electrode is made of a material having a Young's modulus higher than that of the anti-oxidation electrode.
摘要翻译：薄膜电容器具有厚度等于或大于2μm且等于或小于100μm的基板; 所述基板上的下部电极，在所述高弹性电极上至少包括高弹性电极和抗氧化电极; 第一下电极上的电介质薄膜; 和电介质薄膜上的上电极; 其中所述高弹性电极由杨氏模量高于所述抗氧化电极的杨氏模量的材料制成。

5. 发明申请

US20150034373A1 WIRING STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：接线结构及其制造方法
公开(公告)号：US20150034373A1
公开(公告)日：2015-02-05
申请号：US14379420
申请日：2013-02-13
申请人： Yoshiki Nakashima , Masahiro Kubo , Akinobu Shibuya
发明人： Yoshiki Nakashima , Masahiro Kubo , Akinobu Shibuya
IPC分类号： H05K3/12 , H05K1/03 , H05K1/09
CPC分类号： H05K3/1275 , H05K1/0313 , H05K1/09 , H05K3/4685 , H05K2201/0129 , H05K2201/0137 , H05K2203/0278 , Y10T29/49155
摘要： A wiring structure includes a substrate, a convexoconcave absorption layer including a convexoconcave portion on the substrate, a conductive layer pattern on at least a concave portion of the convexoconcave absorption layer, and an insulating layer pattern over the conductive layer pattern and the convexoconcave absorption layer, on at least the concave portion. This configuration provides a wiring structure and a manufacturing method thereof which enable to form fine multilayer wiring using microcontact printing or the like.
摘要翻译：布线结构包括基板，在基板上包括凸凹部的凸凹陷波吸收层，凹凸吸收层的至少凹部的导电层图案，以及导电层图案和凹凸吸收层之上的绝缘层图案至少在凹部上。这种结构提供了使用微接触印刷等形成精细多层布线的布线结构及其制造方法。

6. 发明申请

US20130012145A1 RADIO MODULE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：无线电模块及其制造方法
公开(公告)号：US20130012145A1
公开(公告)日：2013-01-10
申请号：US13636576
申请日：2011-03-15
申请人： Akinobu Shibuya , Akira Ouchi , Akira Miyata , Ryo Miyazaki , Yoshiaki Wakabayashi
发明人： Akinobu Shibuya , Akira Ouchi , Akira Miyata , Ryo Miyazaki , Yoshiaki Wakabayashi
IPC分类号： H04B1/38
CPC分类号： H01P5/024 , H01L23/48 , H01L23/49827 , H01L23/49833 , H01L2223/6627 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2924/00014 , H01L2924/15311 , H01P3/12 , H05K1/0239 , H05K1/141 , H05K2201/096 , H05K2201/09854 , H05K2201/09981 , H01L2224/0401
摘要： Provided is a radio module that includes a radio signal connection portion having a low insertion loss and high reliability.This radio module includes a first wiring substrate 1, and a second wiring substrate 2 which is located opposite to a first face 1a of the first wiring substrate 1. Further, at least one through hole 3 having an inner wall formed of a conductive material is provided inside the second wiring substrate. Moreover, at least one hollow pillar 4 formed of a conductive material is provided at a position corresponding to the at least one through hole 3, on at least one of the first face 1a and a second face 2a of the second wiring substrate 2, the second face 2a being opposite to the first face 1a. Here, an axis-direction height of the at least one hollow pillar 4 formed of a conductive material is smaller than the width of a gap between the first face 1a and the second face 2a. Further, one end face of the at least one hollow pillar 4 formed of a conductive material is not fixed, and a radio signal passes through a hollow portion of the at least one pillar.
摘要翻译：提供一种无线电模块，其包括具有低插入损耗和高可靠性的无线电信号连接部分。该无线电模块包括第一布线基板1和与第一布线基板1的第一面1a相对的第二布线基板2.此外，具有由导电材料形成的内壁的至少一个通孔3是设置在第二布线基板的内部。此外，在与第二布线基板2的第一面1a和第二面2a中的至少一个相对应的至少一个通孔3的位置处设置由导电材料形成的至少一个中空柱4，第二面2a与第一面1a相对。这里，由导电材料形成的至少一个中空柱4的轴向高度小于第一面1a和第二面2a之间的间隙的宽度。此外，由导电材料形成的至少一个中空柱4的一个端面不固定，并且无线电信号通过至少一个支柱的中空部分。

7. 发明授权

US06703705B2 Semiconductor device and method for packaging same 失效
标题翻译：半导体器件及其封装方法
公开(公告)号：US06703705B2
公开(公告)日：2004-03-09
申请号：US09996054
申请日：2001-11-28
申请人： Takao Yamazaki , Toru Mori , Akinobu Shibuya , Shintaro Yamamichi , Yuzo Shimada
发明人： Takao Yamazaki , Toru Mori , Akinobu Shibuya , Shintaro Yamamichi , Yuzo Shimada
IPC分类号： H01L2352
CPC分类号： H01L24/81 , H01L23/50 , H01L23/642 , H01L24/73 , H01L2224/13144 , H01L2224/16 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/19106 , H01L2924/30105 , H01L2924/30107
摘要： A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.
摘要翻译：半导体器件具有在电路形成面的周边部分设置有多个电源线连接焊盘和接地线连接焊盘的LSI器件，电连接到每个焊盘并粘附到LSI的金属箔引线5 通过绝缘层的器件，以及安装在金属箔引线的一个表面上的去耦电容器。

8. 发明授权

US08669138B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08669138B2
公开(公告)日：2014-03-11
申请号：US13549001
申请日：2012-07-13
申请人： Akinobu Shibuya , Koichi Takemura , Akira Ouchi , Tomoo Murakami
发明人： Akinobu Shibuya , Koichi Takemura , Akira Ouchi , Tomoo Murakami
IPC分类号： H01L21/60
CPC分类号： H01L21/563 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L23/295 , H01L23/3121 , H01L23/3128 , H01L24/16 , H01L24/32 , H01L24/81 , H01L24/97 , H01L2221/68377 , H01L2224/05147 , H01L2224/05568 , H01L2224/05573 , H01L2224/0558 , H01L2224/05644 , H01L2224/05655 , H01L2224/16225 , H01L2224/16235 , H01L2224/32057 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/81801 , H01L2224/83385 , H01L2224/97 , H01L2924/01004 , H01L2924/01006 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0106 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/14 , H01L2924/15788 , H01L2924/18165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2224/81 , H01L2924/00 , H01L2924/01031 , H01L2924/3512 , H01L2924/00014
摘要： A substrate and a semiconductor chip are connected by means of flip-chip interconnection. Around connecting pads of the substrate and input/output terminals of the semiconductor chip, an underfill material is injected. The underfill material is a composite material of filler and resin. Also, a first main surface of the substrate, which is not covered with the underfill material, and the side surfaces of the semiconductor chip are encapsulated with a molding material. The molding material is a composite material of filler and resin. An integrated body of the substrate and the semiconductor chip, which are covered with the molding material, is thinned from above and below.
摘要翻译：衬底和半导体芯片通过倒装芯片互连连接。在衬底的连接焊盘和半导体芯片的输入/输出端子之间，注入底部填充材料。底部填充材料是填料和树脂的复合材料。此外，未被底部填充材料覆盖的基板的第一主表面和半导体芯片的侧表面被模制材料封装。成型材料是填料和树脂的复合材料。由模制材料覆盖的衬底和半导体芯片的集成体从上方和下方变薄。

9. 发明授权

US08621730B2 Capacitor producing method for producing thin-film capacitors eliminating defects 失效
标题翻译：制造消除缺陷的薄膜电容器的电容器制造方法
公开(公告)号：US08621730B2
公开(公告)日：2014-01-07
申请号：US13203018
申请日：2010-02-12
申请人： Akinobu Shibuya , Koichi Takemura , Takashi Manako
发明人： Akinobu Shibuya , Koichi Takemura , Takashi Manako
IPC分类号： H01G7/00
CPC分类号： H01G7/00 , H01L22/14 , H01L22/20 , H01L27/016 , H01L2924/0002 , Y10T29/43 , Y10T29/435 , H01L2924/00
摘要： In a capacitor producing method, a bottom electrode, a thin-film dielectric, and a top electrode are deposited on a substrate so as to form a capacitor, wherein defects including particles and electrical short-circuits between the bottom electrode and the top electrode are detected before the capacitor is divided into capacitor cells. Next, defects such as particles and electrical short-circuits between the bottom electrode and the top electrode are removed before the capacitor is divided into capacitor cells.
摘要翻译：在电容器制造方法中，在基板上沉积底电极，薄膜电介质和顶电极以形成电容器，其中包括在底电极和顶电极之间的颗粒和电短路的缺陷是在电容器分为电容器单元之前检测。接下来，在将电容器分成电容器单元之前，去除在底部电极和顶部电极之间的诸如颗粒和电气短路的缺陷。

10. 发明授权

US06618694B1 Method, apparatus and computer program product for forming data to be analyzed by finite element method and calculation method based on finite element method 失效
标题翻译：用有限元分析法形成数据的方法，设备和计算机程序产品，以及基于有限元法的计算方法
公开(公告)号：US06618694B1
公开(公告)日：2003-09-09
申请号：US09084108
申请日：1998-05-26
申请人： Akinobu Shibuya , Kouji Matsui , Hidehito Matsuyama
发明人： Akinobu Shibuya , Kouji Matsui , Hidehito Matsuyama
IPC分类号： G06F1750
CPC分类号： G06T17/20 , G06F17/5018 , G06F2217/80
摘要： A user uses part data forming means 101 and module data forming means 102 to input the actual dimension, physical constants and mesh dividing number for fundamental shapes which are registered in advance, thereby forming parts, and then indicates the relative position between the parts to form the entire shape of an assembly of plural parts without paying attention to coincidence or non-coincidence of nodal points. Data converting means 104 divides the shape of each part thus assembled according to the indicated mesh divisional number to generate element data and nodal point data. Further, it generates a constraint equation for connecting nodal points which are non-connected between neighboring parts, and forms an analysis model 401. A finite element method analyzer 105 uses approximate calculation means 106 to approximate a non-connected nodal point displacement from a nodal point displacement of neighboring structural elements on the basis of the constraint equation.
摘要翻译：用户使用部件数据形成装置101和模块数据形成装置102输入预先登记的基本形状的实际尺寸，物理常数和网格划分数，从而形成零件，然后指示部件之间的相对位置，以形成多个部分的组合的整体形状，而不注意节点的巧合或非重合。数据转换装置104根据指示的网格划分数来划分如此组装的每个部分的形状，以生成元素数据和节点数据。此外，它产生用于连接在相邻部分之间不连接的节点的约束方程，并且形成分析模型401.有限元方法分析器105使用近似计算装置106近似来自节点的非连接节点位移基于约束方程的相邻结构元素的点位移。

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