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1. 发明申请

US20080291987A1 Test Signal Generating Apparatus for Communications Equipment and Test Signal Generating Method for Communications Equipment 有权
标题翻译：通信设备的测试信号发生装置和通信设备的测试信号生成方法
公开(公告)号：US20080291987A1
公开(公告)日：2008-11-27
申请号：US11579644
申请日：2006-04-06
申请人： Akihisa Kumaki , Ikuya Otani , Norihiro Akiyama
发明人： Akihisa Kumaki , Ikuya Otani , Norihiro Akiyama
IPC分类号： H04B17/00
CPC分类号： H04B17/0085
摘要： A test signal generating apparatus for communications equipment sequentially uses first and second sequence information which are stored in a sequence memory for storing the first sequence information including a reading order and read addresses of unit data including I and Q waveform data, and desired signal levels to be set to the unit data, and the second sequence information including frequency offsets. Consequently, the test signal generating apparatus provides frequency offsets at a plurality of steps every predetermined frequency intervals by using a predetermined carrier frequency as a reference, with respect to the I and Q waveform data at a digital stage up to digital-to-analog converters, and outputs a test signal in the frequency hopping system.
摘要翻译：用于通信设备的测试信号发生装置顺序地使用存储在序列存储器中的第一和第二序列信息，用于存储包括读取顺序的第一序列信息和包括I和Q波形数据的单元数据的读取地址以及期望的信号电平被设置为单位数据，第二序列信息包括频率偏移。因此，测试信号生成装置相对于数字级的数字到数字模拟转换器的I和Q波形数据，以预定的载波频率作为参考，以预定的频率间隔在多个步骤中提供频率偏移并在跳频系统中输出测试信号。

2. 发明授权

US07668234B2 Test signal generating apparatus for communications equipment and test signal generating method for communications equipment 有权
标题翻译：用于通信设备的测试信号发生装置和通信设备的测试信号生成方法
公开(公告)号：US07668234B2
公开(公告)日：2010-02-23
申请号：US11579644
申请日：2006-04-06
申请人： Akihisa Kumaki , Ikuya Otani , Norihiro Akiyama
发明人： Akihisa Kumaki , Ikuya Otani , Norihiro Akiyama
IPC分类号： H04B3/46
CPC分类号： H04B17/0085
摘要： A test signal generating apparatus for communications equipment sequentially uses first and second sequence information which are stored in a sequence memory for storing the first sequence information including a reading order and read addresses of unit data including I and Q waveform data, and desired signal levels to be set to the unit data, and the second sequence information including frequency offsets. Consequently, the test signal generating apparatus provides frequency offsets at a plurality of steps every predetermined frequency intervals by using a predetermined carrier frequency as a reference, with respect to the I and Q waveform data at a digital stage up to digital-to-analog converters, and outputs a test signal in the frequency hopping system.
摘要翻译：用于通信设备的测试信号发生装置顺序地使用存储在序列存储器中的第一和第二序列信息，用于存储包括读取顺序的第一序列信息和包括I和Q波形数据的单元数据的读取地址以及期望的信号电平被设置为单位数据，第二序列信息包括频率偏移。因此，测试信号生成装置相对于数字级的数字到数字模拟转换器的I和Q波形数据，以预定的载波频率作为参考，以预定的频率间隔在多个步骤中提供频率偏移并在跳频系统中输出测试信号。

3. 发明授权

US5808493A Rational frequency division device and frequency synthesizer using the same 失效
标题翻译：合理的分频装置和频率合成器使用相同的
公开(公告)号：US5808493A
公开(公告)日：1998-09-15
申请号：US809022
申请日：1997-03-12
申请人： Norihiro Akiyama , Hirokazu Yanagawa , Hatsuo Motoyama
发明人： Norihiro Akiyama , Hirokazu Yanagawa , Hatsuo Motoyama
IPC分类号： G06F7/68 , H03L7/197 , H03L7/06
CPC分类号： G06F7/68 , H03L7/1976
摘要： A rational frequency division device eliminates spurious components by a simple arrangement and can set a broad frequency modulation range. A frequency synthesizer using the rational frequency division device includes an arithmetic circuit, which outputs the frequency division ratio to a frequency divider in a PLL circuit constituted by a variable frequency oscillator 4, a frequency divider 6, and a phase detector 2. The arithmetic circuit includes a plurality of series-connected cumulative adders 22 which include a first cumulative adder that receives a rational number defined by an integer value and a decimal value, an integer value extraction circuit 23 for extracting an integer value from the output value of the cumulative adder of the final stage, and a delay circuit 24 for outputting the integer value extracted by the integer value extraction circuit to the frequency divider as the frequency division ratio, and outputting the integer value to the respective cumulative adders as a feedback value. Each cumulative adder adds a value calculated by itself in the previous clock period to the input rational number or the output value from the cumulative adder of the previous stage, and subtracts the feedback value from the delay circuit therefrom, thus outputting the calculated value.
摘要翻译： PCT No.PCT / JP96 / 02143 Sec。 371日期1997年3月12日 102（e）1997年3月12日PCT PCT 1996年7月30日PCT公布。出版物WO97 / 06600 日期1997年2月20日合理的分频装置通过简单的布置消除杂散分量，并可以设置宽的频率调制范围。使用有理分频装置的频率合成器包括：运算电路，其将分频比输出到由可变频率振荡器4，分频器6和相位检测器2构成的PLL电路中的分频器。运算电路包括多个串联连接的累积加法器22，其包括接收由整数值和十进制值定义的有理数的第一累积加法器，用于从累积加法器的输出值中提取整数值的整数值提取电路23 以及用于将由整数值提取电路提取的整数值输出到分频器的延迟电路24作为分频比，并将整数值作为反馈值输出到各累积加法器。每个累积加法器将在前一时钟周期中自己计算的值与前一级的累积加法器的输入有理数或输出值相加，并从其延迟电路中减去反馈值，从而输出计算值。

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