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    • 3. 发明授权
    • Semiconductor gate array device
    • 半导体门阵列器件
    • US6160275A
    • 2000-12-12
    • US692253
    • 1996-08-05
    • Yoji NishioYasuo KaminagaIsamu KobayashiYoshihiko YamamotoNozomi HorinoKousaku Hirose
    • Yoji NishioYasuo KaminagaIsamu KobayashiYoshihiko YamamotoNozomi HorinoKousaku Hirose
    • H01L27/118H01L27/10
    • H01L27/11807
    • In order to present a basic cell of a master slice type LSI having a high memory density and a high speed logic circuitry, a basic cell is composed of each pair of the PMOS 1, NMOS 4, PMOS 7, and NMOS 10, and three contact holes--besides the contact holes 17, as the contact holes within the MOS channel width W of each MOS, that are connected to the GND power lines 51 and 53, or the Vcc power lines 50 and 52--are formed in the direction perpendicular to each of the power lines. Additionally, in order to present a semiconductor integrated device having a static type RAM that has realized with its simple structure a shortening of the memory cycle, a RAM is constructed by having memory cells, in which each is composed of a pair of transfer MOSFETs, which both of the MOSFETs are turned on during the write-in operation and one of the MOSFETs is turned on during the read-out operation, is located in between a complementary data line and an input/output node that has a complementary relationship with an information storage part comprised by a pair of inverter circuits in which the inputs and outputs are mutually cross-connected. By constructing in this way, it becomes possible to speed up the write-in operation with accuracy by having a complementary write-in signal received from a pair of the complementary lines during the read-out operation, and it becomes possible to obtain read-out signals rapidly and to prevent write-in errors caused by the pre-read-out potential of the data line because the information storage part is connected only to one of the data lines through one of the transfer gates during the read-out operation.
    • 为了呈现具有高存储密度和高速逻辑电路的主片式LSI的基本单元,基本单元由每对PMOS 1,NMOS 4,PMOS 7和NMOS 10组成,并且三个 接触孔 - 除了接触孔17之外,因为连接到GND电源线51和53或Vcc电源线50和52的每个MOS的MOS沟道宽度W内的接触孔形成在垂直方向上 到每个电力线。 此外,为了呈现具有通过其简单结构实现的具有简化结构的静态型RAM的半导体集成器件,缩短了存储器周期,RAM通过具有存储单元构成,其中每个存储单元由一对转移MOSFET组成, 其中两个MOSFET在写入操作期间导通,并且在读出操作期间MOSFET中的一个导通,位于互补数据线与具有互补关系的输入/输出节点之间 信息存储部分由输入和输出相互交叉连接的一对反相器电路组成。 通过以这种方式构造,可以通过在读出操作期间具有从一对互补线接收的互补写入信号来准确地加速写入操作,并且可以获得读取操作, 并且防止由于数据线的预读出电位引起的写入错误,因为信息存储部分在读出操作期间仅通过一个传输门连接到一条数据线。