专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06576923B2 Inspectable buried test structures and methods for inspecting the same 有权
公开(公告)号：US06576923B2
公开(公告)日：2003-06-10
申请号：US10178329
申请日：2002-06-21
申请人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
发明人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
IPC分类号： H01L2358
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S977/712 , Y10S977/723 , Y10S977/888 , Y10S977/89 , H01L2924/00
摘要： Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

2. 发明授权

US06921672B2 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06921672B2
公开(公告)日：2005-07-26
申请号：US10338936
申请日：2003-01-07
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： G01N21/66 , G01N21/95 , G01N21/956 , G01R31/28 , G01R31/307 , H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

3. 发明授权

US06528818B1 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06528818B1
公开(公告)日：2003-03-04
申请号：US09648380
申请日：2000-08-25
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： H01L2358
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

4. 发明授权

US06509197B1 Inspectable buried test structures and methods for inspecting the same 有权
公开(公告)号：US06509197B1
公开(公告)日：2003-01-21
申请号：US09648212
申请日：2000-08-25
申请人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
发明人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
IPC分类号： H01L2100
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

5. 发明授权

US06445199B1 Methods and apparatus for generating spatially resolved voltage contrast maps of semiconductor test structures 有权
标题翻译：用于生成半导体测试结构的空间分辨电压对比图的方法和装置
公开(公告)号：US06445199B1
公开(公告)日：2002-09-03
申请号：US09648379
申请日：2000-08-25
申请人： Akella V. S. Satya , Brian C. Leslie , Gustavo A. Pinto , Robert Thomas Long , Neil Richardson , Bin-Ming Benjamin Tsai
发明人： Akella V. S. Satya , Brian C. Leslie , Gustavo A. Pinto , Robert Thomas Long , Neil Richardson , Bin-Ming Benjamin Tsai
IPC分类号： G01R31308
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a method of inspecting a sample. The sample is illuminated with an incident beam, thereby causing voltage contrast within structures present on the sample. Voltage contrast is detected within the structures. Information from the detected voltage contrast is stored, and position data concerning the location of features corresponding to at least a portion of the stored voltage contrast information is also stored. In a specific embodiment, the features represent electrical defects present on the sample. In another embodiment, the stored position data is in the form of a two dimensional map. In another aspect, the sample is re-inspected and the stored position data is used in analyzing data resulting from the re-inspection.
摘要翻译：公开了一种检查样品的方法。样品用入射光照射，从而在样品中存在的结构内引起电压对比。在结构内检测到电压对比度。存储来自检测到的电压对比度的信息，并且还存储与存储的电压对比度信息的至少一部分相对应的特征位置的位置数据。在具体实施例中，特征表示样品上存在的电缺陷。在另一个实施例中，存储的位置数据是二维地图的形式。在另一方面，重新检查样本，并且将存储的位置数据用于分析由重新检查产生的数据。

6. 发明授权

US07179661B1 Chemical mechanical polishing test structures and methods for inspecting the same 有权
标题翻译：化学机械抛光试验结构及检验方法
公开(公告)号：US07179661B1
公开(公告)日：2007-02-20
申请号：US09648095
申请日：2000-08-25
申请人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
发明人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
IPC分类号： H01L21/00
CPC分类号： H01L22/34
摘要： Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
摘要翻译：公开了一种具有多个虚拟填料的半导体管芯，其中所述多个虚拟填料的位置和尺寸被设计成使化学机械抛光期间的缺陷最小化。虚拟填充物中的至少一个耦合到底层测试结构。在优选实施例中，半导体管芯还包括多个导电层和衬底。下面的测试结构包括由多个导电层中的第一个形成的第一层部分和将第一层部分连接到至少一个虚拟填充物的通孔。在另一方面，基础测试结构还具有将第一层部分耦合到衬底的通孔，并且底层测试结构包括多个层部分和通孔以形成多层测试结构。

7. 发明授权

US07655482B2 Chemical mechanical polishing test structures and methods for inspecting the same 有权
标题翻译：化学机械抛光试验结构及检验方法
公开(公告)号：US07655482B2
公开(公告)日：2010-02-02
申请号：US11621512
申请日：2007-01-09
申请人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
发明人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
IPC分类号： H01L21/00
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
摘要翻译：公开了一种具有多个虚拟填料的半导体管芯，其中所述多个虚拟填料的位置和尺寸被设计成使化学机械抛光期间的缺陷最小化。虚拟填充物中的至少一个耦合到底层测试结构。在优选实施例中，半导体管芯还包括多个导电层和衬底。下面的测试结构包括由多个导电层中的第一个形成的第一层部分和将第一层部分连接到至少一个虚拟填充物的通孔。在另一方面，基础测试结构还具有将第一层部分耦合到衬底的通孔，并且底层测试结构包括多个层部分和通孔以形成多层测试结构。

8. 发明授权

US07656170B2 Multiple directional scans of test structures on semiconductor integrated circuits 有权
标题翻译：半导体集成电路测试结构的多方向扫描
公开(公告)号：US07656170B2
公开(公告)日：2010-02-02
申请号：US11675013
申请日：2007-02-14
申请人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Padma A. Satya, legal representative , Robert Thomas Long , David J. Walker
发明人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
IPC分类号： G01R31/02
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.
摘要翻译：公开了一种检查样品的方法。用至少一个粒子束沿第一方向扫描样品。用至少一个粒子束在第二个方向上扫描样品。第二方向与第一方向成一个角度。作为第一扫描的结果，发现样品的每个区域的缺陷数，并且从第二次扫描确定发现的一个或多个缺陷的位置。在具体实施例中，样本包括其上具有多个测试元件的测试结构。测试元件的第一部分在第一次扫描期间暴露于光束以识别具有缺陷的测试元件，并且第二部分测试元件在第二次扫描期间暴露以分离和表征缺陷。

9. 发明授权

US06867606B2 Multiple directional scans of test structures on semiconductor integrated circuits 有权
公开(公告)号：US06867606B2
公开(公告)日：2005-03-15
申请号：US10390502
申请日：2003-03-13
申请人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
发明人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
IPC分类号： G01N21/66 , G01N21/95 , G01N21/956 , G01N23/04 , G01Q30/16 , G01Q60/44 , G01R31/28 , G01R31/307 , H01L23/544 , G01R31/304
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01N23/04 , G01R31/2884 , G01R31/307 , H01J2237/2817 , Y10S977/849
摘要： Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.

10. 发明授权

US07012439B2 Multiple directional scans of test structures on semiconductor integrated circuits 有权
标题翻译：半导体集成电路测试结构的多方向扫描
公开(公告)号：US07012439B2
公开(公告)日：2006-03-14
申请号：US11058943
申请日：2005-02-15
申请人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
发明人： Gustavo A. Pinto , Brian C. Leslie , David L. Adler , Akella V. S. Satya , Robert Thomas Long , David J. Walker
IPC分类号： G01R31/304
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01N23/04 , G01R31/2884 , G01R31/307 , H01J2237/2817 , Y10S977/849
摘要： Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect.
摘要翻译：公开了一种检查样品的方法。用至少一个粒子束沿第一方向扫描样品。用至少一个粒子束在第二个方向上扫描样品。第二方向与第一方向成一个角度。作为第一扫描的结果，发现样品的每个区域的缺陷数，并且从第二次扫描确定发现的一个或多个缺陷的位置。在具体实施例中，样本包括其上具有多个测试元件的测试结构。测试元件的第一部分在第一次扫描期间暴露于光束以识别具有缺陷的测试元件，并且第二部分测试元件在第二次扫描期间暴露以分离和表征缺陷。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式