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1. 发明授权

US06751519B1 Methods and systems for predicting IC chip yield 有权
标题翻译：用于预测IC芯片产量的方法和系统
公开(公告)号：US06751519B1
公开(公告)日：2004-06-15
申请号：US10281433
申请日：2002-10-24
申请人： Akella V. S. Satya , Li Song , Robert Thomas Long , Kurt H. Weiner
发明人： Akella V. S. Satya , Li Song , Robert Thomas Long , Kurt H. Weiner
IPC分类号： G06F1900
CPC分类号： H01L22/20 , G01R31/2894 , G01R31/307 , H01L22/14 , H01L22/34
摘要： Disclosed are methods and apparatus for efficiently managing IC chip yield learning. In general terms, as each wafer lot moves through fabrication, yield information is obtained from each set of test structures for a particular process or defect mechanism. The nature of the yield information is such that it may be used directly or indirectly to predict product wafer test yield. In one implementation, the yield information includes a systematic yield (Y0), a defect density (DD), and a defect clustering factor (&agr;) determined based on the inspected test structure's yield. A running average of the yield information for each process or defect mechanism is maintained as each wafer lot is processed. As a particular wafer lot moves through the various processes, a product wafer-sort test yield may be predicted at any stage in the fabrication process based on the running-average yield information maintained for previously fabricated wafer lots.
摘要翻译：公开了用于有效管理IC芯片产量学习的方法和装置。一般来说，随着每个晶片批次移动通过制造，从特定工艺或缺陷机制的每组测试结构获得产量信息。产量信息的性质可以直接或间接地用于预测产品晶圆测试产量。在一个实施方案中，产量信息包括基于检验的测试结构的产量确定的系统产量（Y0），缺陷密度（DD）和缺陷聚类因子（α）。当处理每个晶片批时，维持每个处理或缺陷机制的产量信息的运行平均值。随着特定的晶片批次移动通过各种工艺，可以基于为先前制造的晶片批次保持的运行平均产量信息，在制造过程的任何阶段预测产品晶圆分选测试产量。

2. 发明授权

US06921672B2 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06921672B2
公开(公告)日：2005-07-26
申请号：US10338936
申请日：2003-01-07
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： G01N21/66 , G01N21/95 , G01N21/956 , G01R31/28 , G01R31/307 , H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

3. 发明授权

US06528818B1 Test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：用于半导体集成电路检查的测试结构和方法
公开(公告)号：US06528818B1
公开(公告)日：2003-03-04
申请号：US09648380
申请日：2000-08-25
申请人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
发明人： Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
IPC分类号： H01L2358
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

4. 发明授权

US06636064B1 Dual probe test structures for semiconductor integrated circuits 有权
标题翻译：半导体集成电路的双探针测试结构
公开(公告)号：US06636064B1
公开(公告)日：2003-10-21
申请号：US09648092
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Neil Richardson , Kurt H. Weiner , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Neil Richardson , Kurt H. Weiner , David J. Walker
IPC分类号： G01R3128
CPC分类号： H01L22/34 , G01N21/66 , G01N21/9501 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817
摘要： Disclosed is a semiconductor die having an upper layer and a lower layer. The die includes a lower test structure formed in the lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end, wherein the first end is coupled to a predetermined voltage level. The die also has an insulating layer formed over the lower metal layer and an upper test structure formed in the upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure, and the upper metal layer being formed over the insulating layer. The die further includes at least one probe pad coupled with the upper test structure. Preferably, the first end of the lower test structure is coupled to a nominal ground potential. In another implementation, the upper test structure is a voltage contrast element. In another embodiment, a semiconductor die having a scanning area is disclosed. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The die includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The first plurality of test structures or the second plurality of test structures has a probe pad coupled to at least one test structure.
摘要翻译：公开了具有上层和下层的半导体管芯。模具包括形成在半导体管芯的下金属层中的下部测试结构。下导电测试结构具有第一端和第二端，其中第一端耦合到预定的电压电平。模具还具有形成在下金属层上的绝缘层和形成在半导体管芯的上金属层中的上测试结构。上导电测试结构与下导电测试结构的第二端耦合，并且上金属层形成在绝缘层上。芯片还包括与上测试结构耦合的至少一个探针焊盘。优选地，下测试结构的第一端耦合到标称接地电位。在另一实施方案中，上测试结构是电压对比元件。在另一实施例中，公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。模具包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分地位于扫描区域内。第一多个测试结构或第二多个测试结构具有耦合到至少一个测试结构的探针焊盘。

5. 发明授权

US06813572B2 Apparatus and methods for managing reliability of semiconductor devices 有权
标题翻译：用于管理半导体器件的可靠性的装置和方法
公开(公告)号：US06813572B2
公开(公告)日：2004-11-02
申请号：US10281432
申请日：2002-10-24
申请人： Akella V.S. Satya , Li Song , Robert Thomas Long , Kurt H. Weiner
发明人： Akella V.S. Satya , Li Song , Robert Thomas Long , Kurt H. Weiner
IPC分类号： G06F1900
CPC分类号： G01R31/287 , G01R31/2831 , G01R31/2856 , G01R31/2858 , G01R31/2894
摘要： Disclosed are methods and apparatus for determining whether to perform burn-in on a semiconductor product, such as a product wafer or product wafer lot. In general terms, test structures on the semiconductor product are inspected to extract yield information, such as defect densities. Since this yield information is related to the early or extrinsic instantaneous failure rate, one may then determine the instantaneous extrinsic failure rate for one or more failure mechanisms, such as electromigration, gate oxide breakdown, or hot carrier injection, based on this yield information. It is then determined whether to perform burn-in on the semiconductor product based on the determined instantaneous failure rate.
摘要翻译：公开了用于确定是否对诸如产品晶片或产品晶片批次的半导体产品进行老化的方法和装置。通常，检查半导体产品上的测试结构以提取诸如缺陷密度的产量信息。由于该产量信息与早期或非本征瞬时故障率相关，因此可以基于该产量信息来确定一个或多个故障机制的瞬时外在故障率，例如电迁移，栅极氧化物分解或热载流子注入。然后，根据所确定的瞬时故障率，确定是否对半导体产品进行老化。

6. 发明申请

US20080246030A1 TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS 审中-公开
标题翻译：用于检查半导体集成电路的测试结构和方法
公开(公告)号：US20080246030A1
公开(公告)日：2008-10-09
申请号：US11675021
申请日：2007-02-14
申请人： Akella V.S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas , Padma A. Satya
发明人： Akella V.S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas , Padma A. Satya
IPC分类号： H01L23/58 , H01L21/00
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
摘要翻译：公开了具有扫描区域的半导体管芯。半导体管芯包括第一多个测试结构，其中第一多个测试结构中的每个测试结构完全位于扫描区域内。半导体管芯还包括第二多个测试结构，其中第一多个测试结构中的每个测试结构仅部分位于扫描区域内。测试结构被布置成使得扫描区域的扫描导致检测到扫描区域外的缺陷。

7. 发明授权

US08343327B2 Apparatus and methods for fast chemical electrodeposition for fabrication of solar cells 有权
标题翻译：快速化学电沉积制造太阳能电池的装置和方法
公开(公告)号：US08343327B2
公开(公告)日：2013-01-01
申请号：US12787330
申请日：2010-05-25
申请人： Kurt H. Weiner , Gaurav Verma
发明人： Kurt H. Weiner , Gaurav Verma
IPC分类号： C25D5/10 , C25D5/00 , C25D17/00
CPC分类号： C25D5/022 , C25D5/08 , C25D17/001 , C25D17/005 , C25D17/12
摘要： The invention relates generally to electrodeposition apparatus and methods. When depositing films via electrodeposition, where the substrate has an inherent resistivity, for example, sheet resistance in a thin film, methods and apparatus of the invention are used to electrodeposit materials onto the substrate by forming a plurality of ohmic contacts to the substrate surface and thereby overcome the inherent resistance and electrodeposit uniform films. Methods and apparatus of the invention find particular use in solar cell fabrication.
摘要翻译：本发明一般涉及电沉积装置和方法。当通过电沉积沉积膜时，其中衬底具有固有电阻率，例如薄膜中的薄层电阻，本发明的方法和装置用于通过在衬底表面上形成多个欧姆接触将材料电沉积到衬底上，从而克服固有的电阻和电沉积均匀的膜。本发明的方法和装置在太阳能电池制造中特别有用。

8. 发明授权

US08207069B2 Advanced mixing method for integrated tool having site-isolated reactors 有权
标题翻译：具有现场隔离反应堆的综合工具的先进混合方法
公开(公告)号：US08207069B2
公开(公告)日：2012-06-26
申请号：US13189894
申请日：2011-07-25
申请人： Kurt H. Weiner , Tony P. Chiang , Aaron Francis , John Schmidt
发明人： Kurt H. Weiner , Tony P. Chiang , Aaron Francis , John Schmidt
IPC分类号： H01L21/00 , H01L21/306 , C40B50/00 , C40B60/00
CPC分类号： C23C16/45514 , C23C16/45574 , C23C16/52 , H01L21/67017 , H01L21/67276 , Y10S438/907 , Y10S438/908 , Y10S438/913 , Y10T137/4673 , Y10T137/469 , Y10T137/87249 , Y10T137/87265 , Y10T137/87281
摘要： An integrated processing tool is described comprising a full-wafer processing module and a combinatorial processing module. Chemicals for use in the combinatorial processing module are fed from a delivery system including a set of first manifolds. An output of each first manifold is coupled to at least one mixing vessel. An output of each mixing vessel feeds more than one of a set of second manifolds. An output of each set of second manifolds feeds one of multiple site-isolated reactors of the combinatorial processing module.
摘要翻译：描述了一种集成处理工具，其包括全晶片处理模块和组合处理模块。用于组合处理模块的化学品从包括一组第一歧管的递送系统进料。每个第一歧管的输出端连接至至少一个混合容器。每个混合容器的输出馈送一组第二歧管中的多于一个。每组第二歧管的输出馈送组合处理模块的多个位置隔离反应器中的一个。

9. 发明申请

US20070267631A1 System and Method for Increasing Productivity of Combinatorial Screening 有权
标题翻译：提高组合筛选生产力的系统和方法
公开(公告)号：US20070267631A1
公开(公告)日：2007-11-22
申请号：US11419174
申请日：2006-05-18
申请人： Kurt H. Weiner , Tony P. Chiang , Gustavo A. Pinto
发明人： Kurt H. Weiner , Tony P. Chiang , Gustavo A. Pinto
IPC分类号： H01L23/58
CPC分类号： H01L22/10 , H01L21/67005 , H01L22/34
摘要： The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.
摘要翻译：本发明提供用于同时，并行和/或快速连续测试材料参数或过程结果的其它参数的系统和方法。测试通常用于筛选不同的方法或材料以选择具有所需性质的那些方法或材料。用于形成材料的反应器结构可以由覆盖在基板上的小的分离的反应室的阵列组成，使得基板形成每个分离的反应室的底表面。在基板上形成测试结构，其中每个测试结构的位置对应于反应结构的分离的反应室区域。测试结构用于测量某些参数，例如通过探测每个测试结构的接触垫，或者可以在处理期间原位进行这种测试。

10. 发明授权

US07067335B2 Apparatus and methods for semiconductor IC failure detection 有权
公开(公告)号：US07067335B2
公开(公告)日：2006-06-27
申请号：US10264625
申请日：2002-10-02
申请人： Kurt H. Weiner , Gaurav Verma
发明人： Kurt H. Weiner , Gaurav Verma
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L22/34 , G01N21/9501 , G01R31/2644 , G01R31/307
摘要： An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure. To produce different voltage potentials, a first set of substructures are coupled to a relatively large conductive structure, such as a large conductive pad, so that the first set of substructures charges more slowly than a second set of substructures that are not coupled to the relatively large conductive structure. Mechanisms for fabricating such a test structure are also disclosed. Additionally, searching mechanisms for quickly locating defects within such a test structure, as well as other types of voltage contrast structures, during a voltage contrast inspection are also provided.

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