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1. 发明授权

US06261467B1 Direct deposit thin film single/multi chip module 失效
标题翻译：直接沉积薄膜单/多芯片模块
公开(公告)号：US06261467B1
公开(公告)日：2001-07-17
申请号：US09427753
申请日：1999-10-27
申请人： Ajay P. Giri , Sundar M. Kamath , Daniel P. O'Connor , Rajesh B. Patel , Herbert I. Stoller , Lisa M. Studzinski , Paul R. Walling
发明人： Ajay P. Giri , Sundar M. Kamath , Daniel P. O'Connor , Rajesh B. Patel , Herbert I. Stoller , Lisa M. Studzinski , Paul R. Walling
IPC分类号： H05K302
CPC分类号： H01L23/5383 , H01L23/5385 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/15312 , H01L2924/15313 , H01L2924/3011 , H05K1/0306 , H05K1/114 , H05K3/4605 , H05K2201/0154 , H05K2201/09509 , H05K2201/096 , H05K2201/10674 , Y10S428/901 , Y10T428/24917 , H01L2924/00 , H01L2224/0401
摘要： A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer. At least one mounting location suitable for mounting an electronic component is formed on the second dielectric layer. The substrate may be attached a printed circuit board by direct attachment, pin grid array (PGA), land grid array (LGA), ball grid array (BGA), column grid array (CGA) and miniBGA on the bottom layer of the ceramic base.
摘要翻译：用于将集成电路芯片安装到其上的高性能TF陶瓷模块以及以较低成本制造模块的方法。衬底包括直接形成在层状陶瓷基底上的薄膜（TF）层。使用厚膜技术在厚膜层状陶瓷基体的顶表面上形成第一厚膜布线层或嵌入第一厚膜布线层。在第一布线层的顶部上形成聚酰亚胺或其它有机材料的第一介电层或不同于陶瓷材料的绝缘材料。介电层可以旋涂或喷涂并烘烤; 气相沉积层压到陶瓷基体上; 或者使用等离子体增强化学气相沉积（PECVD）沉积无机层。通过第一介电层形成通孔。在第一电介质层上形成第二布线层。第二介电层形成在第二布线层上。在第二电介质层上形成至少一个适于安装电子部件的安装位置。衬底可以通过直接附接的印刷电路板，陶瓷基底的底层上的引脚格栅阵列（PGA），栅格阵列（LGA），球栅阵列（BGA），列网格阵列（CGA）和miniBGA 。

2. 发明授权

US6037044A Direct deposit thin film single/multi chip module 失效
标题翻译：直接沉积薄膜单/多芯片模块
公开(公告)号：US6037044A
公开(公告)日：2000-03-14
申请号：US4690
申请日：1998-01-08
申请人： Ajay P. Giri , Sundar M. Kamath , Daniel P. O'Connor , Rajesh B. Patel , Herbert I. Stoller , Lisa M. Studzinski , Paul R. Walling
发明人： Ajay P. Giri , Sundar M. Kamath , Daniel P. O'Connor , Rajesh B. Patel , Herbert I. Stoller , Lisa M. Studzinski , Paul R. Walling
IPC分类号： H05K1/18 , H01L23/12 , H01L23/32 , H01L23/538 , H05K1/02 , H05K1/03 , H05K1/11 , H05K3/46 , B32B3/00
CPC分类号： H01L23/5383 , H01L23/5385 , H05K1/114 , H01L2224/16225 , H01L2924/00014 , H01L2924/09701 , H01L2924/10253 , H01L2924/15312 , H01L2924/15313 , H01L2924/3011 , H05K1/0306 , H05K2201/0154 , H05K2201/09509 , H05K2201/096 , H05K2201/10674 , H05K3/4605 , Y10S428/901 , Y10T428/24917
摘要： A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer. At least one mounting location suitable for mounting an electronic component is formed on the second dielectric layer. The substrate may be attached a printed circuit board by direct attachment, pin grid array (PGA), land grid array (LGA), ball arid array (BGA), column grid array (CGA) and miniBGA on the bottom layer of the ceramic base.
摘要翻译：用于将集成电路芯片安装到其上的高性能TF陶瓷模块以及以较低成本制造模块的方法。衬底包括直接形成在层状陶瓷基底上的薄膜（TF）层。使用厚膜技术在厚膜层状陶瓷基体的顶表面上形成第一厚膜布线层或嵌入第一厚膜布线层。在第一布线层的顶部上形成聚酰亚胺或其它有机材料的第一介电层或不同于陶瓷材料的绝缘材料。介电层可以旋涂或喷涂并烘烤; 气相沉积层压到陶瓷基体上; 或者使用等离子体增强化学气相沉积（PECVD）沉积无机层。通过第一介电层形成通孔。在第一电介质层上形成第二布线层。第二介电层形成在第二布线层上。在第二电介质层上形成至少一个适于安装电子部件的安装位置。衬底可以通过直接附接的印刷电路板，陶瓷基底的底层上的针格阵列（PGA），平面阵列（LGA），球形阵列（BGA），列网格阵列（CGA）和miniBGA 。

3. 发明授权

US09280473B2 Method and apparatus for accessing physical memory from a CPU or processing element in a high performance manner 有权
标题翻译：用于以高性能方式从CPU或处理元件访问物理存储器的方法和装置
公开(公告)号：US09280473B2
公开(公告)日：2016-03-08
申请号：US11004753
申请日：2004-12-02
申请人： Sanjoy K. Mondal , Rajesh B. Patel , Lawrence O. Smith
发明人： Sanjoy K. Mondal , Rajesh B. Patel , Lawrence O. Smith
IPC分类号： G06F12/08 , G06F9/30 , G06F12/10
CPC分类号： G06F12/0862 , G06F9/30149 , G06F9/3016 , G06F9/30181 , G06F12/0888 , G06F12/10 , G06F12/1027
摘要： A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.
摘要翻译：本文描述了一种用于访问由处理器引用的物理地址的物理存储器位置的方法和装置。处理器通过引用虚拟内存地址和/或对物理地址的引用来获取/接收指令。翻译逻辑将虚拟内存地址转换为物理地址，并将物理地址提供给公共接口。物理寻址逻辑解码对物理地址的引用，并根据物理寻址逻辑存储的存储器类型将物理地址提供给公共接口。

4. 发明授权

US5870577A System and method for dispatching two instructions to the same execution unit in a single cycle 失效
标题翻译：在一个周期内将两条指令分派到相同执行单元的系统和方法
公开(公告)号：US5870577A
公开(公告)日：1999-02-09
申请号：US758066
申请日：1996-11-27
申请人： Rajesh B. Patel , Soummya Mallick , Romesh Mangho Jessani
发明人： Rajesh B. Patel , Soummya Mallick , Romesh Mangho Jessani
IPC分类号： G06F9/38
CPC分类号： G06F9/30167 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3857
摘要： When the instruction dispatch unit detects two consecutive immediate instructions in the instruction queue directed to the same execution unit, it dispatches both during the same cycle, making use of both GPR ports for the two required GPR operands. Instruction path directing logic directs the first instruction to the execution decoder of the one execution unit during the first occurring cycle and latches the second instruction until a second occurring cycle. It also directs the first immediate operand of the first instruction to a first input of an execution block in the one execution unit during the first occurring cycle. An operand path directing logic directs the first GPR operand referred to by the first instruction to a second input of the execution block during the first occurring cycle and latches a second GPR operand referred to by the second instruction until the second occurring cycle. The instruction path directing logic directs the second instruction to the execution decoder during the second occurring cycle and directs the second immediate operand of the second instruction to the first input of the execution block during the second occurring cycle. The operand path directing logic directs the second GPR operand to the second input of the execution block during the second occurring cycle. In this manner, two instructions are dispatched in a single cycle from the instruction queue to one execution unit of the multiple execution unit parallel computer.
摘要翻译：当指令调度单元检测到指向同一个执行单元的指令队列中的两个连续的立即指令时，它将在相同的周期内调度两个GPR端口两个所需的GPR操作数。指令路径指令逻辑在第一次出现周期期间将第一指令指向一个执行单元的执行解码器，并将第二指令锁存到第二个发生周期。它还在第一个发生周期中将第一指令的第一个立即操作数定向到一个执行单元中执行块的第一个输入。操作数路径指令逻辑将第一指令引用的第一GPR操作数引导到执行块的第二个输入，并锁存第二指令引用的第二个GPR操作数直到第二个发生周期。指令路径指令逻辑在第二发生周期期间将第二指令指引到执行解码器，并且在第二发生周期期间将第二指令的第二立即操作数引导到执行块的第一输入。操作数路径定向逻辑在第二次发生周期期间将第二GPR操作数引导到执行块的第二个输入。以这种方式，从指令队列到多个执行单元并行计算机的一个执行单元的单个周期中分派两个指令。

5. 发明授权

US07269711B2 Methods and apparatus for address generation in processors 有权
标题翻译：处理器中地址生成的方法和设备
公开(公告)号：US07269711B2
公开(公告)日：2007-09-11
申请号：US10747764
申请日：2003-12-29
申请人： Rajesh B. Patel , Robert L. Farrell , James E. Phillips , Belliappa Kuttanna , Scott E. Siers , T. W. Griffith
发明人： Rajesh B. Patel , Robert L. Farrell , James E. Phillips , Belliappa Kuttanna , Scott E. Siers , T. W. Griffith
IPC分类号： G06F12/00
CPC分类号： G06F9/342 , G06F9/355 , G06F9/3842 , G06F9/3861
摘要： Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.
摘要翻译：公开了在处理器中产生地址的方法和装置。本文公开的示例性地址生成器包括：加法器，用于添加第一地址分量和第二地址分量以产生地址;校正指示符，用于指示地址是否正确;以及控制输入，用于修改加法器的操作。

6. 发明授权

US5897654A Method and system for efficiently fetching from cache during a cache fill operation 失效
标题翻译：高速缓存填充操作期间从高速缓存中有效提取的方法和系统
公开(公告)号：US5897654A
公开(公告)日：1999-04-27
申请号：US881223
申请日：1997-06-24
申请人： Lee E. Eisen , Belliappa M. Kuttanna , Soummya Mallick , Rajesh B. Patel
发明人： Lee E. Eisen , Belliappa M. Kuttanna , Soummya Mallick , Rajesh B. Patel
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0859 , G06F12/0862
摘要： A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions or data words into a cache. In response to each individual instruction or data word being loaded into the cache by the bus interface unit, there is an indication that the individual one of said plurality of instructions or data words is valid. Once a desired instruction or data word has an indication that it is valid, the fetcher is allowed to complete a fetch operation prior to all of the instructions or data words being loaded into cache. In one embodiment, a group of invalid tag bits may be utilized to indicate to the fetcher that individual ones of a group of instructions or data words are valid in cache after being written into cache by the bus interface unit.
摘要翻译：数据处理系统中的一种方法和系统，用于通过在多个数据字或指令被加载到高速缓存中允许读取器从高速缓冲存储器中读取来高效地与高速缓存存储器连接。总线接口单元请求将多个指令或数据字加载到高速缓存中。响应于由总线接口单元加载到高速缓存中的每个单独指令或数据字，存在所述多个指令或数据字中的单个指令或数据字有效的指示。一旦所需的指令或数据字具有有效的指示，则在所有指令或数据字被加载到高速缓存之前，允许提取器完成取指操作。在一个实施例中，一组无效标签位可以被用于在由总线接口单元写入高速缓存之后向读取器指示一组指令或数据字中的各个有效。

7. 发明授权

US5802340A Method and system of executing speculative store instructions in a parallel processing computer system 失效
标题翻译：在并行处理计算机系统中执行推测存储指令的方法和系统
公开(公告)号：US5802340A
公开(公告)日：1998-09-01
申请号：US518000
申请日：1995-08-22
申请人： Soummya Mallick , Rajesh B. Patel
发明人： Soummya Mallick , Rajesh B. Patel
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A method for speculatively performing store instructions in a parallel processing computer system, the computer system including a completion buffer unit, includes comparing statuses between a first store instruction and at least one second instruction in the completion buffer unit, the at least one second instruction scheduled for completion before the first store instruction, and speculatively completing the first store instruction before the at least one second instruction when the statuses of the first store instruction do not conflict with the at least one second instruction. In another method aspect, speculatively performing store instructions includes forming a general purpose register (GPR) allocation deallocation table, the table including status fields for a plurality of instructions in a completion buffer unit, comparing the status fields of each of the plurality of instructions to a store instruction of the plurality of instructions, and speculatively completing the store instruction when the status fields for the store instruction do not conflict with the status fields for the plurality of instructions.
摘要翻译：一种用于在并行处理计算机系统中推测性地执行存储指令的方法，所述计算机系统包括完成缓冲器单元，包括比较第一存储指令与完成缓冲器单元中的至少一个第二指令之间的状态，所述至少一个第二指令被调度在第一存储指令之前完成，并且当第一存储指令的状态不与至少一个第二指令冲突时，在至少一个第二指令之前推测地完成第一存储指令。在另一方法方面，推测性地执行的存储指令包括形成通用寄存器（GPR）分配解除分配表，该表包括完成缓冲器单元中的多个指令的状态字段，将多个指令中的每一个的状态字段与多个指令的存储指令，并且当存储指令的状态字段不与多个指令的状态字段冲突时，推测地完成存储指令。

8. 发明授权

US5765215A Method and system for efficient rename buffer deallocation within a processor 失效
标题翻译：处理器内高效重命名缓冲区释放的方法和系统
公开(公告)号：US5765215A
公开(公告)日：1998-06-09
申请号：US519556
申请日：1995-08-25
申请人： Muhammad Afsar , Soummya Mallick , Rajesh B. Patel
发明人： Muhammad Afsar , Soummya Mallick , Rajesh B. Patel
IPC分类号： G06F9/312 , G06F9/38 , G06F9/26 , G06F12/02
CPC分类号： G06F9/30043 , G06F9/3836 , G06F9/384
摘要： A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions executed by the processor, a number of registers, and a memory. According to the present invention, an update instruction is dispatched to the processor for execution. A particular rename buffer is then allocated to the update instruction. An effective address is generated for the update instruction, wherein the effective address specifies an address within the memory to be accessed by the update instruction. Next, the effective address is stored within the particular rename buffer. Prior to completion of the access to the effective address within memory, the effective address is transferred from the particular rename buffer to a particular one of the number of registers. Thereafter, the particular rename buffer is deallocated, wherein processor performance is enhanced by improved rename buffer availability.
摘要翻译：公开了一种用于管理分配给处理器内的更新指令的重命名缓冲器的分配的方法和系统。处理器具有多个重命名缓冲器，用于临时存储与由处理器执行的指令相关联的信息，多个寄存器和存储器。根据本发明，更新指令被发送到处理器执行。然后将特定的重命名缓冲区分配给更新指令。生成更新指令的有效地址，其中，有效地址指定要由更新指令访问的存储器内的地址。接下来，有效地址存储在特定的重命名缓冲区内。在访问存储器内的有效地址之前，将有效地址从特定重命名缓冲区传送到寄存器数目中的特定一个。此后，取消分配特定重命名缓冲区，其中通过改进的重命名缓冲器可用性来增强处理器性能。

9. 发明申请

US20130191603A1 Method And Apparatus For Accessing Physical Memory From A CPU Or Processing Element In A High Performance Manner 审中-公开
标题翻译：用于以高性能方式从CPU或处理元件访问物理内存的方法和装置
公开(公告)号：US20130191603A1
公开(公告)日：2013-07-25
申请号：US13795247
申请日：2013-03-12
申请人： Sanjoy K. Mondal , Rajesh B. Patel , Lawrence O. Smith
发明人： Sanjoy K. Mondal , Rajesh B. Patel , Lawrence O. Smith
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F9/30149 , G06F9/3016 , G06F9/30181 , G06F12/0888 , G06F12/10 , G06F12/1027
摘要： A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.
摘要翻译：本文描述了一种用于访问由处理器引用的物理地址的物理存储器位置的方法和装置。处理器通过引用虚拟内存地址和/或对物理地址的引用来获取/接收指令。翻译逻辑将虚拟内存地址转换为物理地址，并将物理地址提供给公共接口。物理寻址逻辑解码对物理地址的引用，并根据物理寻址逻辑存储的存储器类型将物理地址提供给公共接口。

10. 发明授权

US5809323A Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor 失效
标题翻译：用于在超标量处理器的空闲执行单元内执行定点指令的方法和装置
公开(公告)号：US5809323A
公开(公告)日：1998-09-15
申请号：US530552
申请日：1995-09-19
申请人： Lee E. Eisen , Robert T. Golla , Soummya Mallick , Sung-Ho Park , Rajesh B. Patel , Michael Putrino
发明人： Lee E. Eisen , Robert T. Golla , Soummya Mallick , Sung-Ho Park , Rajesh B. Patel , Michael Putrino
IPC分类号： G06F9/302 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/3836 , G06F9/384
摘要： A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the present invention, a set of instructions to be executed are fetched from among a number of instructions stored within memory. A determination is then made if n instructions, the maximum number possible, can be dispatched to the multiple execution units during a first processor cycle if fixed point arithmetic and logical instructions are dispatched only to the FXU. If so, n instructions are dispatched to the multiple execution units for execution. In response to a determination that n instructions cannot be dispatched during the first processor cycle, a determination is made whether a fixed point instruction is available to be dispatched and whether dispatching the fixed point instruction to the non-FXU for execution will result in greater efficiency. In response to a determination that a fixed point instruction is not available to be dispatched or that dispatching the fixed point instruction to the non-FXU will not result in greater efficiency, dispatch of the fixed point instruction is delayed until a second processor cycle. However, in response to a determination that dispatching the fixed point instruction to the non-FXU will result in greater efficiency, the fixed point instruction is dispatched to the non-FXU and executed, thereby improving execution unit utilization.
摘要翻译：公开了一种用于在超标量处理器内执行定点指令的超标量处理器和方法。超标量处理器具有存储器和多个执行单元，包括固定点执行单元（FXU）和非固定点执行单元（非FXU）。根据本发明，从存储在存储器中的多个指令中取出要执行的一组指令。然后如果将固定点算术和逻辑指令仅发送到FXU，则可以在第一处理器周期期间将n个指令（尽可能最大数）分派到多个执行单元进行确定。如果是这样，n个指令被分派到多个执行单元执行。响应于在第一处理器周期期间不能调度n个指令的确定，确定是否可以调度固定点指令，以及是否向非FXU分派定点指令以执行将导致更高的效率。响应于确定不能发送固定点指令或者将定点指令分派到非FXU不会导致更高的效率，所以定点指令的调度被延迟到第二处理器周期。然而，响应于将定点指令发送到非FXU的确定将导致更高的效率，将定点指令分派到非FXU并执行，从而提高执行单元的利用率。

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