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1. 发明授权

US06546539B1 Netlist resynthesis program using structure co-factoring 有权
标题翻译：网表再合成程序使用结构协同分解
公开(公告)号：US06546539B1
公开(公告)日：2003-04-08
申请号：US09736571
申请日：2000-12-14
申请人： Aiquo Lu , Ivan Pavisic , Pedja Raspopovic
发明人： Aiquo Lu , Ivan Pavisic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/505
摘要： A program for improving a netlist of logic nodes and physical placement for an IC. The program (A) identifies critical nodes based on time calculated from a physical placement. The program (B) selects a set of critical nodes and sub-netlists associated with the critical nodes and co-factors critical fan-ins in the sub-netlists. The program remaps the sub-netlists by optimization and dynamically estimates and updates fanout loads. The program returns to step B if the remapped sub-netlist is unacceptable, returns to step A if the remapped sub-netlist is acceptable, and exits at step A when no more critical nodes are identified at step A.
摘要翻译：用于改进IC的逻辑节点和物理放置的网表的程序。程序（A）基于从物理位置计算的时间来识别关键节点。程序（B）选择与关键节点相关联的一组关键节点和子网表，并在子网表中选择关联扇区的关键扇区。该程序通过优化重新映射子网表，并动态估计和更新扇出负载。如果重新映射的子网表不可接受，则程序返回到步骤B，如果重新映射的子网表可接受，则返回到步骤A，并且在步骤A没有在步骤A没有识别出更多的关键节点时退出步骤A.

2. 发明授权

US06412102B1 Wire routing optimization 失效
标题翻译：电线路由优化
公开(公告)号：US06412102B1
公开(公告)日：2002-06-25
申请号：US09120617
申请日：1998-07-22
申请人： Alexander Andreev , Ivan Pavisic , Pedja Raspopovic
发明人： Alexander Andreev , Ivan Pavisic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： The invention is directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a set of areas, and a boundary pin is defined at each point on a boundary of one of the areas where the boundary of the one of the areas intersects a net. Routing optimization is then performed in at least one of the areas, the routing optimization optimizing the routing among the net pins and the boundary pins within the at least one of the areas. The invention is also directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a first set of pre-defined areas, and routing optimization is performed independently in each of the pre-defined areas in the first set. The surface is divided into a second set of pre-defined areas, and routing optimization is performed independently in each of the pre-defined areas in the second set. It is a feature of this aspect of the invention that each of plural pre-defined areas in the first set overlaps at least two pre-defined areas in the second set, and each of plural pre-defined areas in the second set overlaps at least two pre-defined areas in the first set.
摘要翻译：本发明涉及一种将网络连接在一个表面上的初始路由的优化，每个网络包括多个互连的网络引脚。表面被划分成一组区域，并且在一个区域的边界与网络相交的区域之一的边界上的每个点处定义边界销。然后在至少一个区域中执行路由优化，路由优化优化网内引脚和该至少一个区域内的边界引脚之间的路由。本发明还涉及将网络连接在表面上的初始路由的优化，每个网络包括多个互连的网络引脚。表面被划分成第一组预定义区域，并且在第一组中的每个预定义区域中独立地执行路由优化。表面被划分成第二组预定义区域，并且在第二组中的每个预定义区域中独立地执行路由优化。本发明的这个方面的特征在于，第一组中的多个预定义区域中的每一个与第二组中的至少两个预定义区域重叠，并且第二组中的多个预定义区域中的每一个至少重叠第一组中的两个预定义区域。

3. 发明授权

US06182272B2 Metal layer assignment 失效
标题翻译：金属层分配
公开(公告)号：US06182272B2
公开(公告)日：2001-01-30
申请号：US09118661
申请日：1998-07-16
申请人： Alexander Andreev , Ivan Pavisic , Pedja Raspopovic
发明人： Alexander Andreev , Ivan Pavisic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Routing layers are assigned to connection segments in integrated circuit design. A routing description that includes connection segments and a vertex where at least two of the connection segments connect to each other is obtained. A penalty is determined for the vertex based on a potential layer assignment combination for the connection segments that connect at the vertex, and routing layers are assigned to the connection segments based on the determined penalty.
摘要翻译：路由层被分配到集成电路设计中的连接段。获得包括连接段和至少两个连接段彼此连接的顶点的路由描述。基于针对在顶点连接的连接段的潜在层分配组合，确定顶点的惩罚，并且基于确定的罚分将路由层分配给连接段。

4. 发明授权

US06463572B1 IC timing analysis with known false paths 有权
标题翻译：具有已知虚路径的IC时序分析
公开(公告)号：US06463572B1
公开(公告)日：2002-10-08
申请号：US09871129
申请日：2001-05-31
申请人： Ivan Pavisic , Pedja Raspopovic , Aiguo Lu
发明人： Ivan Pavisic , Pedja Raspopovic , Aiguo Lu
IPC分类号： G06F945
CPC分类号： G06F17/5031
摘要： True paths are identified in a timing graph of a circuit in which the timing graph contains known false paths containing nodes of at least two sets selected from FROM, THROUGH and TO nodes. The false paths are processed to include sets of FROM and TO nodes and then transformed into equivalent sets of two logical false paths. True path intervals are constructed as logical subgraphs that do not describe any equivalent false path. In preferred embodiments, the process is carried out by a computer under control of a computer readable program.
摘要翻译：真实路径在电路的时序图中被识别，其中定时图包含包含从FROM，THROUGH和TO节点中选择的至少两个集合的节点的已知虚路径。处理伪路径以包括FROM和TO节点的集合，然后转换成两个逻辑假路径的等效集合。真实路径间隔被构造为不描述任何等效假路径的逻辑子图。在优选实施例中，该过程由计算机在计算机可读程序的控制下执行。

5. 发明授权

US06269469B1 Method and apparatus for parallel routing locking mechanism 失效
标题翻译：并行路由锁定机制的方法和装置
公开(公告)号：US06269469B1
公开(公告)日：2001-07-31
申请号：US09062418
申请日：1998-04-17
申请人： Ivan Pavisic , Ranko Scepanovic , Pedja Raspopovic
发明人： Ivan Pavisic , Ranko Scepanovic , Pedja Raspopovic
IPC分类号： H03K17693
CPC分类号： G06F17/5077
摘要： A method for implementing net routing for an integrated circuit design with parallel processors, said method comprising the steps of creating a character array, filling said character array with a first character, dividing a plurality of nets into groups, supplying a plurality of locks and assigning each said group its own individual lock, assigning for each net in said plurality of nets a position in the character array; and placing a second character in the position of a particular net in said character array when the net is operated on by a processor and replacing said second character with the first character after said operation is completed.
摘要翻译：一种用于实现具有并行处理器的集成电路设计的网络路由的方法，所述方法包括以下步骤：创建字符阵列，用第一字符填充所述字符阵列，将多个网络划分成组，提供多个锁定和分配每个所述组别自己的个人锁定，为所述多个网络中的每个网络分配字符阵列中的位置; 以及当所述网络由处理器操作并且在所述操作完成之后用所述第一字符替换所述第二字符时，将第二字符放置在所述字符阵列中的特定网络的位置。

6. 发明授权

US06557144B1 Netlist resynthesis program based on physical delay calculation 失效
标题翻译：基于物理延迟计算的网表再合成程序
公开(公告)号：US06557144B1
公开(公告)日：2003-04-29
申请号：US09737239
申请日：2000-12-14
申请人： Aiguo Lu , Ivan Pavisic , Pedja Raspopovic
发明人： Aiguo Lu , Ivan Pavisic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5072
摘要： A computer program that improves a netlist of logic nodes and physical placement for an IC. The program (a) identifies critical nodes based on delay information calculated from the physical placement. Then the program (b) selects a set of critical nodes and optimally collapses their critical fan-ins and part of the non-critical fan-ins based on their Boolean relationship, which, includes at least one critical node. After that, the program (c) remaps the collapsed sub-netlist by covering its subject graph with an optimal pattern graph, and dynamically estimates and updates the fanout loads. The program returns to step (b) if the remapped sub-netlist is unacceptable, and returns to step (a) after updating the delay information and coordinates of newly mapped gates if the remapped sub-netlist is acceptable. The program exits at step (a) when no more critical nodes are identified at step (a).
摘要翻译：一种改进逻辑节点网表和IC物理放置的计算机程序。程序（a）基于从物理位置计算的延迟信息来识别关键节点。然后，程序（b）选择一组关键节点，并根据其布尔关系最佳地折叠其关键扇区和非关键扇区的一部分，其中至少包括一个关键节点。之后，程序（c）通过用最佳模式图覆盖其主题图来重新映射折叠的子网表，并动态地估计并更新扇出负载。如果重新映射的子网表不可接受，则程序返回到步骤（b），并且如果重新映射的子网表是可接受的，则在更新延迟信息和新映射的门的坐标之后返回到步骤（a）。步骤（a），当在步骤（a）中没有更多关键节点被识别时，该程序退出。

7. 发明授权

US06643832B1 Virtual tree-based netlist model and method of delay estimation for an integrated circuit design 有权
标题翻译：基于虚拟树的网表模型和集成电路设计的延迟估计方法
公开(公告)号：US06643832B1
公开(公告)日：2003-11-04
申请号：US09964011
申请日：2001-09-26
申请人： Partha P. Data Ray , Mikhail I. Grinchuk , Pedja Raspopovic
发明人： Partha P. Data Ray , Mikhail I. Grinchuk , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A pre-placement delay model for a logical function block of an integrated circuit design includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.
摘要翻译：用于集成电路设计的逻辑功能块的预放置延迟模型包括扇入计数变量，扇出计数变量和延迟变量。扇入计数变量具有指示逻辑功能块的输入的数量的值。扇出计数变量具有指示由逻辑功能块的输出驱动的其他逻辑功能块的输入的数量的值。延迟变量具有作为扇入计数变量的二进制对数和扇出计数变量的二进制对数的值。

8. 发明授权

US06324674B2 Method and apparatus for parallel simultaneous global and detail routing 失效
标题翻译：并行同时全局和细节路由的方法和装置
公开(公告)号：US06324674B2
公开(公告)日：2001-11-27
申请号：US09062309
申请日：1998-04-17
申请人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
发明人： Alexander E. Andreev , Elyar E. Gasanov , Ranko Scepanovic , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.
摘要翻译：一种用于在集成电路设计中布线网络的方法，所述方法包括以下步骤：将集成电路设计与沿第一方向和第二方向的线分开，形成具有顶点和边缘的路由图，其中顶点对应于第一方向上的线在第二方向上交叉线，将并行网络作为所述路由图的函数，并行处理器基本上同时运行，确定集成电路设计中的不同区域之间的相对电线拥塞，以及重新路由通过区域的网络电线拥塞比较高

9. 发明授权

US06154874A Memory-saving method and apparatus for partitioning high fanout nets 失效
标题翻译：用于分割高扇出网络的存储器保存方法和装置
公开(公告)号：US06154874A
公开(公告)日：2000-11-28
申请号：US62219
申请日：1998-04-17
申请人： Ranko Scepanovic , Alexander E. Andreev , Pedja Raspopovic
发明人： Ranko Scepanovic , Alexander E. Andreev , Pedja Raspopovic
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： An object of the present invention is to provide for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements. Said elementary pairs are identified by determining for each pin in said net a relative x-coordinate and a relative y-coordinate, constructing for each pin a combined binary coordinate as a function of the pin's relative x-coordinate and relative y-coordinate, ordering the pins in accordance with their respective combined binary coordinates, iteratively combining the pins until one pin remains, and iteratively expanding the pins.
摘要翻译：本发明的目的是提供一种将高扇出网分成较小子网的方法和装置。所述方法包括以下步骤：识别网中的基本对引脚，每个这样的基本对定义一条线; 消除形成平面图形的线条; 消除形成生成树的更多的线，所述生成树连接网中的每个引脚; 识别基本元素，形成所述生成树的一部分的每个基本元素; 以及构建所述网的连接的盖，所述连接的盖包括多个所述基本元件。通过确定所述网中的每个针的相对x坐标和相对的y坐标来识别所述基本对，所述相对的x坐标和相对的y坐标构成了作为销的相对x坐标和相对y坐标的函数的组合二进制坐标根据它们各自组合的二进制坐标的引脚，迭代地组合引脚直到保持一个引脚，并且迭代地扩展引脚。

10. 发明授权

US08843865B2 Data flow analyzer 有权
标题翻译：数据流分析仪
公开(公告)号：US08843865B2
公开(公告)日：2014-09-23
申请号：US13405302
申请日：2012-02-26
申请人： Philip H. Tai , Pedja Raspopovic , Jaime Wong
发明人： Philip H. Tai , Pedja Raspopovic , Jaime Wong
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and method for generating physical design of an integrated circuit, based on schematic design. The system includes graphical user interface and integrated circuit design and layout system. The integrated circuit design and layout system creates and analyzes logical slices of the integrated circuit based on the schematic design; creates and edits macros based on the logical slices; and traces and analyzes data paths through the physical design based on the schematic design. The method includes providing the schematic design of the integrated circuit, and generating logical slices of the integrated circuit from the schematic design. The method also includes generating, grouping and manipulating macros, responsive to identification of multiple occurrences of logical slices. The method further includes performing data flow analysis to identify data paths for the physical design, quantifying weight indices for the data paths, and positioning objects in the physical design based on the weight indices.
摘要翻译：基于原理图设计的用于生成集成电路的物理设计的系统和方法。该系统包括图形用户界面和集成电路设计和布局系统。集成电路设计和布局系统基于原理图设计创建和分析集成电路的逻辑片段; 基于逻辑切片创建和编辑宏; 并通过基于原理图设计的物理设计跟踪和分析数据路径。该方法包括提供集成电路的原理图设计，并从原理图设计生成集成电路的逻辑片。该方法还包括响应于多次出现的逻辑切片的识别而生成，分组和操纵宏。该方法还包括执行数据流分析以识别用于物理设计的数据路径，量化数据路径的权重索引，以及基于权重索引在物理设计中定位对象。

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