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1. 发明授权

US08735857B2 Via-configurable high-performance logic block architecture 有权
标题翻译：通过可配置的高性能逻辑块架构
公开(公告)号：US08735857B2
公开(公告)日：2014-05-27
申请号：US13271679
申请日：2011-10-12
申请人： Alexander Andreev , Sergey Gribok , Ranko Scepanovic
发明人： Alexander Andreev , Sergey Gribok , Ranko Scepanovic
IPC分类号： H01L27/08 , H01L47/00
CPC分类号： H03K19/17728 , H03K19/17796
摘要： A via-configurable circuit block may contain chains of p-type and n-type transistors that may or may not be interconnected by means of configurable vias. Configurable vias may also be used to connect various transistor terminals to a ground line, a power line and/or to various terminals that may provide connections outside of the circuit block.
摘要翻译：通孔可配置电路块可以包含可以或可以不通过可配置通孔互连的p型和n型晶体管链。可配置的通孔也可用于将各种晶体管端子连接到接地线，电力线和/或可提供电路块外部的连接的各种端子。

2. 发明授权

US08443033B2 Variable node processing unit 失效
标题翻译：可变节点处理单元
公开(公告)号：US08443033B2
公开(公告)日：2013-05-14
申请号：US12185404
申请日：2008-08-04
申请人： Alexander Andreev , Sergey Gribok , Oleg Izyumin
发明人： Alexander Andreev , Sergey Gribok , Oleg Izyumin
IPC分类号： G06F7/50 , H03M13/00
CPC分类号： G06F7/575 , H03M13/1102 , H03M13/1111 , H03M13/1117
摘要： A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series.
摘要翻译：具有N + 1个输入的可变节点处理单元，其具有至少第一组双输入加法器和独立的最后一组双输入加法器，其中加法器组串联设置。

3. 发明授权

US08250129B2 Cryptographic random number generator using finite field operations 失效
标题翻译：加密随机数发生器使用有限域操作
公开(公告)号：US08250129B2
公开(公告)日：2012-08-21
申请号：US11821212
申请日：2007-06-22
申请人： Sergey Gribok , Alexander Andreev , Sergey Gashkov
发明人： Sergey Gribok , Alexander Andreev , Sergey Gashkov
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/588 , G06F7/724 , H04L9/0861
摘要： An apparatus and method are provided in various illustrative embodiments for an integrated circuit chip that provides a fast, compact, and cryptographically strong random number generator. In one illustrative embodiment, an apparatus includes an initial random source, and a post-processing block in communicative connection with the initial random source. The post-processing block is configured to receive signals from the initial random source, to apply one or more finite field operations to the signals to generate an output, and to provide an output signal based on the output via an output channel, in this illustrative embodiment.
摘要翻译：在提供快速，紧凑和密码强的随机数发生器的集成电路芯片的各种说明性实施例中提供了一种装置和方法。在一个说明性实施例中，装置包括初始随机源和与初始随机源通信连接的后处理块。后处理块被配置为从初始随机源接收信号，以将一个或多个有限场操作应用于信号以产生输出，并且在该说明性视图中通过输出通道提供基于输出的输出信号实施例。

4. 发明申请

US20110099454A1 Low Complexity LDPC Encoding Algorithm 审中-公开
标题翻译：低复杂度LDPC编码算法
公开(公告)号：US20110099454A1
公开(公告)日：2011-04-28
申请号：US12985850
申请日：2011-01-06
申请人： Sergey Gribok , Alexander Andreev , Igor Vikhliantsev
发明人： Sergey Gribok , Alexander Andreev , Igor Vikhliantsev
IPC分类号： H03M13/00 , G06F11/00
CPC分类号： H03M13/116 , H03M13/1185
摘要： A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a matrix formed only of circulant permutation sub matrices, and D is a matrix of the form D = ( T 0 … 0 0 0 T … 0 0 … … … … … 0 0 … T 0 I I … I I ) where T is a two-diagonal, circulant sub matrix, and I is an identity sub matrix.
摘要翻译：通过计算x：= Au来计算二进制源消息u，计算y：= B'x，解析p的等式Dp = y，并且并入u和p以产生编码的二进制消息v，其中A是一个仅由置换子矩阵构成的矩阵，B'是仅由循环置换子矩阵形成的矩阵，D是形式为D =（T 0 ... 0 0 0 T ... 0 0 ...... ...... 0 0 ... T 0 II ... II）其中T是双对角，循环子矩阵，I是身份子矩阵。

5. 发明授权

US07823050B2 Low area architecture in BCH decoder 有权
标题翻译： BCH解码器中的低域架构
公开(公告)号：US07823050B2
公开(公告)日：2010-10-26
申请号：US11613529
申请日：2006-12-20
申请人： Elyar E. Gasanov , Alexander Andreev , Ilya V. Neznanov , Pavel A. Panteleev , Sergei Gashkov
发明人： Elyar E. Gasanov , Alexander Andreev , Ilya V. Neznanov , Pavel A. Panteleev , Sergei Gashkov
IPC分类号： H03M13/00
CPC分类号： H03M13/1555 , H03M13/152 , H03M13/153 , H03M13/158
摘要： An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t−1)/(codeword_len−3)≦X
摘要翻译：对于BCH解码器的关键方程求解器块的改进，其中密钥方程求解器块具有由X指定的乘数单元数，其中：t *（7 * t-1）/（codeord_len-3）＆nlE; X < （t + 1），其中t是用于校正密钥方程求解器块的传输错误的数目，而code_len是由BCH解码器解码的发送码字的长度。

6. 发明授权

US07739471B2 High performance tiling for RRAM memory 有权
标题翻译：高性能平铺的RRAM内存
公开(公告)号：US07739471B2
公开(公告)日：2010-06-15
申请号：US11256830
申请日：2005-10-24
申请人： Alexander Andreev , Igor Vikhliantsev , Ranko Scepanovic
发明人： Alexander Andreev , Igor Vikhliantsev , Ranko Scepanovic
IPC分类号： G06F12/02
CPC分类号： G11C8/12 , G11C2207/104
摘要： A method of configuring a random access memory matrix containing partially configured memories in the matrix. The method includes the steps of independently calculating a memory enable signal and a configuration signal for a partially configured memory in each memory tile of the memory matrix. Memory tiles not supported by a memory compiler are determined. A memory wrapper is provided for each tile not supported by the memory compiler. An address controller is inserted in the memory matrix for each tile in a group of tiles. Output signals from each memory location in a memory group having a common group index are combined into a single output signal. A first stripe of memory tiles containing non-configured memory having a first width is selected. A second strip of memory tiles containing configured memory having a second width is also selected.
摘要翻译：一种在矩阵中配置包含部分配置的存储器的随机存取存储器矩阵的方法。该方法包括以下步骤：对存储器矩阵的每个存储器块中的部分配置的存储器独立地计算存储器使能信号和配置信号。确定内存编译器不支持的内存片。为存储器编译器不支持的每个片提供内存包装器。在一组瓦片中的每个瓦片的存储矩阵中插入地址控制器。来自具有公共组索引的存储器组中的每个存储器位置的输出信号被组合成单个输出信号。选择包含具有第一宽度的非配置存储器的第一条存储器片。还选择包含具有第二宽度的配置存储器的第二条存储器片。

7. 发明申请

US20090281969A1 Decision Tree Representation of a Function 有权
标题翻译：函数的决策树表示
公开(公告)号：US20090281969A1
公开(公告)日：2009-11-12
申请号：US12117851
申请日：2008-05-09
申请人： Alexander Andreev , Vojislav Vukovic , Ranko Scepanovic
发明人： Alexander Andreev , Vojislav Vukovic , Ranko Scepanovic
IPC分类号： G06F15/18
CPC分类号： G06F17/505
摘要： An arbitrary function may be represented as an optimized decision tree. The decision tree may be calculated, pruned, and factored to create a highly optimized set of equations, much of which may be represented by simple circuits and little, if any, complex processing. A circuit design system may automate the decision tree generation, optimization, and circuit generation for an arbitrary function. The circuits may be used for processing digital signals, such as soft decoding and other processes, among other uses.
摘要翻译：任意函数可以表示为优化决策树。决策树可以被计算，修剪和因子分解以创建高度优化的方程组，其中大部分可以由简单的电路和很少的（如果有的话）复杂的处理来表示。电路设计系统可以自动执行任意功能的决策树生成，优化和电路生成。这些电路可以用于处理数字信号，诸如软解码和其他处理以及其它用途。

8. 发明授权

US07546505B2 Built in self test transport controller architecture 失效
标题翻译：内置自检传输控制器架构
公开(公告)号：US07546505B2
公开(公告)日：2009-06-09
申请号：US11557513
申请日：2006-11-08
申请人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
发明人： Sergey Gribok , Alexander Andreev , Ivan Pavisic
IPC分类号： G01R31/28 , G11C29/00
CPC分类号： G11C29/16 , G11C29/34 , G11C2029/0401 , G11C2029/1204 , G11C2029/2602
摘要： A built in self test circuit in a memory matrix. Memory cells within the matrix are disposed into columns. The circuit has only one memory test controller, adapted to initiate commands and receive results. Transport controllers are paired with the columns of memory cells. The controllers receive commands from the memory test controller, test memory cells within the column, receive test results, and provide the results to the memory test controller. The transport controllers operate in three modes. A production testing mode tests the memory cells in different columns, accumulating the results for a given column with the controller associated with the column. A production testing mode retrieves the results from the controllers. A diagnostic testing mode tests memory cells within one column, while retrieving results for the column.
摘要翻译：内存自检电路在内存矩阵中。矩阵内的存储单元被排列成列。该电路只有一个内存测试控制器，适用于启动命令并接收结果。传输控制器与存储单元的列配对。控制器从存储器测试控制器接收命令，测试列内的测试存储单元，接收测试结果，并将结果提供给存储器测试控制器。运输控制器以三种模式运行。生产测试模式测试不同列中的存储单元，使用与列相关联的控制器累积给定列的结果。生产测试模式从控制器检索结果。诊断测试模式测试一列内的存储单元，同时检索列的结果。

9. 发明申请

US20080178057A1 PIPELINED LDPC ARITHMETIC UNIT 失效
标题翻译：管道LDPC算法单元
公开(公告)号：US20080178057A1
公开(公告)日：2008-07-24
申请号：US11626400
申请日：2007-01-24
申请人： Alexander Andreev , Vojislav Vukovic , Ranko Scepanovic
发明人： Alexander Andreev , Vojislav Vukovic , Ranko Scepanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/1145
摘要： An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1 representation to a 2*p0−1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module. The second Gallager module converts the result from the 2*p0−1 representation to the p0/p1 representation and the final value leaves the unit as md_g_out. In these calculations, md_R=a check node value from the previous iteration, md_g=an edge value (md_g_in—from the previous iteration, md_g_out—for the next iteration), p0=probability that a value is zero, p1=probability that a value is one, loc_item_in/loc_item_out=intermediate values used for the md_g_out calculation, and hard_out=a bit value estimation for the current iteration of the pipelined arithmetic unit.
摘要翻译：对低密度奇偶校验解码器的算术单元的改进，其中算术单元具有模块的流水线架构。第一模块计算md_R和md_g_in的绝对值之间的差值，并将结果传递给第一个Gallager模块。第一个Gallager模块将该值从p0 / p1表示转换为2 * p0-1表示，并将结果传递给第二个模块。第二个模块根据md_g_in和md_R的符号值有选择地调整前一个模块的结果，并将其一个输出传递给第三个模块（另外两个输出loc_item_out和hard_out不是流水线的一部分）。第三个模块通过添加第二个模块的结果和loc_item_in来计算一个新的md_g值，并将该结果传递给第四个模块。第四个模块分离新的md_g的符号和绝对值，并将结果传递给第二个Gallager模块。第二个Gallager模块将2 * p0-1表示的结果转换为p0 / p1表示，最终值将单位设为md_g_out。在这些计算中，md_R =来自前一次迭代的校验节点值，md_g =边缘值（md_g_in - 来自上一次迭代，md_g_out-用于下一次迭代），p0 =值为零的概率，p1 = 值为1，loc_item_in / loc_item_out =用于md_g_out计算的中间值，hard_out =流水线运算单元当前迭代的位值估计。

10. 发明申请

US20070169009A1 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US20070169009A1
公开(公告)日：2007-07-19
申请号：US11260517
申请日：2005-10-27
申请人： Andrey Nikitin , Alexander Andreev , Ranko Scepanovic
发明人： Andrey Nikitin , Alexander Andreev , Ranko Scepanovic
IPC分类号： G06F9/45
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号，RESET信号，ENABLE信号和N个二进制输入x 1，x 2，。。。并且输出命令和数据的序列。

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