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1. 发明申请

US20050024250A1 Space efficient low power cyclic A/D converter 有权
公开(公告)号：US20050024250A1
公开(公告)日：2005-02-03
申请号：US10631450
申请日：2003-07-30
申请人： Ahmad Atriss , Steven Allen
发明人： Ahmad Atriss , Steven Allen
IPC分类号： H03M1/06 , H03M1/34 , H03M1/40 , H04B20060101
CPC分类号： H03M1/0695 , H03M1/40
摘要： Methods and apparatus are provided for an analog converter. The apparatus comprises a first redundant signed digit (RSD) stage and a configurable block. The configurable block converts to a sample/hold circuit to sample a single ended analog signal. The sampled signal is then scaled, converted to a differential signal and provided to the first RSD stage. The first RSD stage outputs a bit value corresponding to the magnitude of the digital signal. In a next half clock cycle the first RSD stage calculates a residue that is provided to the configurable block. The configurable block is converted to a second redundant signed digit stage and generates a bit value corresponding to the magnitude of the residue provided by the first RSD stage. The first and second RSD stages cycle back and forth generating logic value each half clock cycle until the desired bit resolution is achieved. The configurable block is then converted back to a sample/hold circuit to start another conversion process.

2. 发明申请

US20050219097A1 OPTIMIZED REFERENCE VOLTAGE GENERATION USING SWITCHED CAPACITOR SCALING FOR DATA CONVERTERS 失效
标题翻译：使用切换电容器优化数据转换器的优化参考电压发生器
公开(公告)号：US20050219097A1
公开(公告)日：2005-10-06
申请号：US10804453
申请日：2004-03-19
申请人： Ahmad Atriss , Steven Allen , Douglas Garrity
发明人： Ahmad Atriss , Steven Allen , Douglas Garrity
IPC分类号： H03M1/12 , H03M1/16 , H03M1/66
CPC分类号： H03M1/162
摘要： An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.
摘要翻译：算法或循环数据转换器使用具有开关电容器网络的RSD级，用于有效地缩放至少一个外部提供的参考电压。通过使用电容比例来缩放参考电压，该比率也用作提供用作RSD A / D转换器的残留输出的输出电压。残留物用于产生对应于残基大小的位值。两个RSD阶段来回循环，每半个时钟周期产生一个逻辑值，直到达到所需的位分辨率。在一种形式中，RSD级仅通过小于1的因子来缩放外部提供的参考电压。在另一种形式中，RSD级通过任何缩放因子来缩放参考电压。避免了与RSD级分离的参考电压缩放电路。

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