专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5946588A Low temperature sub-atmospheric ozone oxidation process for making thin gate oxides 失效
标题翻译：用于制造薄栅氧化物的低温亚大气臭氧氧化工艺
公开(公告)号：US5946588A
公开(公告)日：1999-08-31
申请号：US779602
申请日：1997-01-07
申请人： Aftab Ahmad , Randhir P. S. Thakur , J. Brett Rolfson , Brian Benard
发明人： Aftab Ahmad , Randhir P. S. Thakur , J. Brett Rolfson , Brian Benard
IPC分类号： H01L21/28 , H01L21/316 , H01L21/762
CPC分类号： H01L21/28211 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/76216
摘要： A process for making thin gate oxides comprising the layering of a semiconductor substrate with at least an oxide layer and a nitride layer. The layers are then patterned and etched, thereby exposing portions of the substrate. The substrate is then doped, thereby creating a channel stop region. The exposed portions of the substrate are oxidized, thereby creating a field oxide region. The oxide and nitride layers are removed, thereby exposing sites of active areas, and a gate oxide layer grown in an ozone-containing atmosphere.
摘要翻译：一种用于制造薄栅极氧化物的方法，包括至少具有氧化物层和氮化物层的半导体衬底的层叠。然后对这些层进行图案化和蚀刻，从而暴露衬底的部分。然后将衬底掺杂，从而形成通道停止区域。衬底的暴露部分被氧化，从而产生场氧化物区域。去除氧化物和氮化物层，从而暴露有源区的位置，以及在含臭氧的气氛中生长的栅极氧化物层。

2. 发明授权

US5382533A Method of manufacturing small geometry MOS field-effect transistors having improved barrier layer to hot electron injection 失效
标题翻译：制造具有改进的阻挡层到热电子注入的小几何MOS场效应晶体管的方法
公开(公告)号：US5382533A
公开(公告)日：1995-01-17
申请号：US79322
申请日：1993-06-18
申请人： Aftab Ahmad , Randhir P. S. Thakur
发明人： Aftab Ahmad , Randhir P. S. Thakur
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51 , H01L21/265
CPC分类号： H01L29/512 , H01L21/28176 , H01L29/518 , H01L29/6659 , Y10S438/91
摘要： A process for suppressing hot electrons in sub half micron MOS devices wherein a gate oxide and a gate electrode are formed on the surface of a silicon substrate and source and drain regions are ion implanted into the silicon substrate using the gate electrode as a mask. The process includes forming a layer of silicon dioxide over the gate electrode and over the source and drain regions of the substrate, and then introducing a barrier layer forming element into the layer of silicon dioxide to form a thin barrier region to hot electrons at the interface between the silicon substrate and the silicon dioxide. In a preferred embodiment of the invention, nitrogen is introduced into the silicon dioxide by heating the wafer in a rapid thermal processor and in the presence of a nitrogen containing gas at an elevated temperature for a predetermined time. The nitrogen containing gas may be selected from the group consisting of nitrogen trifluoride, ammonia and nitrous oxide. In an alternative embodiment of the invention, fluorine atoms are introduced into the silicon substrate either as the sole barrier layer forming element (silicon fluoride) or prior to the formation of the thin silicon nitride region. The fluorine atoms form good strong silicon-fluorine bonds in the silicon substrate and thereby further enhance the hot electron suppression. In a third embodiment, nitrogen and fluorine are reacted in a rapid thermal processor to form a composite barrier layer of Si.sub.3 N.sub.4 and SF.
摘要翻译：用于抑制半微米MOS器件中的热电子的方法，其中在硅衬底的表面上形成栅极氧化物和栅电极，并且使用栅电极作为掩模将源极和漏极区域离子注入到硅衬底中。该方法包括在栅电极上方和衬底的源极和漏极区上形成二氧化硅层，然后将阻挡层形成元件引入到二氧化硅层中以在界面处形成热电子的薄屏障区在硅衬底和二氧化硅之间。在本发明的一个优选实施方案中，通过在快速热处理器中加热晶片并且在含氮气体存在下在升高的温度下将氮气引入二氧化硅中达预定时间。含氮气体可以选自三氟化氮，氨和一氧化二氮。在本发明的替代实施例中，氟原子作为唯一的阻挡层形成元件（氟化硅）或在形成薄氮化硅区之前被引入到硅衬底中。氟原子在硅衬底中形成良好的强硅 - 氟键，从而进一步增强热电子抑制。在第三实施例中，氮和氟在快速热处理器中反应以形成Si 3 N 4和SF的复合势垒层。

3. 发明授权

US5716862A High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS 失效
标题翻译：采用分裂多晶硅CMOS工艺的高性能PMOSFET，包含用于制造多兆位DRAMS的先进的堆叠电容单元
公开(公告)号：US5716862A
公开(公告)日：1998-02-10
申请号：US491179
申请日：1995-06-16
申请人： Aftab Ahmad , Randhir P. S. Thakur , Kirk Prall , Tyler Lowrey , Brett Rolfson
发明人： Aftab Ahmad , Randhir P. S. Thakur , Kirk Prall , Tyler Lowrey , Brett Rolfson
IPC分类号： H01L21/28 , H01L21/265 , H01L21/02 , H01L21/70 , H01L27/00
CPC分类号： H01L21/28061 , H01L21/28247
摘要： This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. In one embodiment of the present invention teaches a semiconductor manufacturing process for forming p-channel devices by the steps of: defining p-channel transistor gate electrodes having substantially vertical sidewalls over n-well regions; performing a p-type impurity implant into the n-well regions to form p-channel source and drain terminals on opposing sides of each the p-channel transistor gate electrodes; performing an angled n-type impurity implant into the n-well regions to form an n-type halo around the p-channel source and drain terminals; performing a low temperature oxidation step at a temperature ranging between 600.degree.-957.degree. C., to form poly gate sidewall oxidation about the vertical sidewalls of the p-channel transistor gate electrodes; and performing a p-type impurity implant into the n-well regions.
摘要翻译：本发明是使用分裂多晶硅CMOS制造流程中的堆叠容器电容器单元制造动态随机存取存储器的方法。分离多晶硅流程表示使用单独的掩蔽步骤由单个导电层（通常为掺杂多晶硅层）形成N沟道和P沟道晶体管栅极。在本发明的一个实施例中，教导了通过以下步骤形成p沟道器件的半导体制造工艺：定义在n-阱区上具有基本上垂直的侧壁的p沟道晶体管栅电极; 对n阱区域进行p型杂质注入，以在每个p沟道晶体管栅电极的相对侧上形成p沟道源极和漏极端子; 在n阱区域中执行倾斜的n型杂质注入以在p沟道源极和漏极端子周围形成n型光晕; 在600〜957℃的温度范围内进行低温氧化步骤，以形成围绕p沟道晶体管栅极垂直侧壁的多晶硅侧壁氧化; 以及对n阱区进行p型杂质注入。

4. 发明授权

US07176549B2 Shallow trench isolation using low dielectric constant insulator 有权
标题翻译：使用低介电常数绝缘子的浅沟槽隔离
公开(公告)号：US07176549B2
公开(公告)日：2007-02-13
申请号：US11012012
申请日：2004-12-13
申请人： Klaus F. Schuegraf , Aftab Ahmad
发明人： Klaus F. Schuegraf , Aftab Ahmad
IPC分类号： H01L29/00
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A shallow trench isolation is disclosed wherein the trench depth is reduced beyond that achieved in prior art processes. The reduced trench depth helps to eliminate the formation of voids during the trench refill process and provides for greater planarity in the final isolation structure. Effective device isolation is achieved with a reduced trench depth by utilizing refilling dielectric materials having low dielectric constant.
摘要翻译：公开了一种浅沟槽隔离，其中沟槽深度减小到超过现有技术工艺中所达到的深度。减小的沟槽深度有助于在沟槽再填充过程期间消除空隙的形成，并且在最终隔离结构中提供更大的平坦度。通过利用具有低介电常数的再填充介电材料，通过减小沟槽深度实现有效的器件隔离。

5. 发明授权

US06930363B2 Barrier in gate stack for improved gate dielectric integrity 失效
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06930363B2
公开(公告)日：2005-08-16
申请号：US10901552
申请日：2004-07-27
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/49 , H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

6. 发明授权

US06770571B2 Barrier in gate stack for improved gate dielectric integrity 有权
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06770571B2
公开(公告)日：2004-08-03
申请号：US10339731
申请日：2003-01-08
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L2131
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

7. 发明授权

US06743979B1 Bonding pad isolation 有权
标题翻译：粘接垫隔离
公开(公告)号：US06743979B1
公开(公告)日：2004-06-01
申请号：US10652453
申请日：2003-08-29
申请人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H05K506
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.
摘要翻译：一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。还包括最顶层的导电层和底层导电层。外部接合焊盘设置在外圈中，并形成在最上层。内部接合焊盘设置在内圈中，并且形成在最顶层内。内部连接器将内部接合焊盘电连接到电路。内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。外部连接器将外部接合焊盘电连接到电路。外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

8. 发明授权

US06373114B1 Barrier in gate stack for improved gate dielectric integrity 有权
标题翻译：栅极堆叠中的栅极，用于改善栅极电介质完整性
公开(公告)号：US06373114B1
公开(公告)日：2002-04-16
申请号：US09178306
申请日：1998-10-23
申请人： Nanseng Jeng , Aftab Ahmad
发明人： Nanseng Jeng , Aftab Ahmad
IPC分类号： H01L2994
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/823437
摘要： A barrier layer comprising silicon mixed with an impurity is disclosed for protection of gate dielectrics in integrated transistors. In particular, the barrier layer comprises silicon incorporating nitrogen. The nitrogen can be incorporated into an upper portion of the gate polysilicon during deposition, or a silicon layer doped with nitrogen after silicon deposition. The layer is of particular utility in conjunction with CVD tungsten silicide straps.
摘要翻译：公开了包含与杂质混合的硅的阻挡层，用于保护集成晶体管中的栅极电介质。特别地，阻挡层包括掺入氮的硅。在沉积期间可以将氮结合到栅极多晶硅的上部，或在硅沉积之后掺入氮的硅层。该层与CVD钨硅化物带结合是特别实用的。

9. 发明授权

US06281092B1 Method for manufacturing a metal-to-metal capacitor utilizing only one masking step 有权
标题翻译：仅使用一个掩模步骤来制造金属 - 金属电容器的方法
公开(公告)号：US06281092B1
公开(公告)日：2001-08-28
申请号：US09347487
申请日：1999-07-02
申请人： Aftab Ahmad
发明人： Aftab Ahmad
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/3212
摘要： A capacitor is fabricated on a semiconductor substrate by first forming a first capacitor electrode on the semiconductor substrate and forming a planar insulating layer over the first capacitor electrode. A photoresist layer is then formed over the planar insulating layer and patterned utilizing in only masking step to form an opening over the first capacitor electrode. Through the opening, the planar insulating layer is etched, and a capacitor dielectric layer is thereafter formed. A second capacitor electrode is then formed over the capacitor dielectric layer in alignment with the first capacitor electrode. The structure is planarized to expose the planar insulating layer. In a preferred embodiment, a trench in the second capacitor electrode is protected during planarization by a spin-on photoresist that is stripped following planarization.
摘要翻译：在半导体衬底上制造电容器，首先在半导体衬底上形成第一电容器电极，并在第一电容器电极上形成平面绝缘层。然后在平面绝缘层上形成光致抗蚀剂层，并且仅在掩模步骤中利用图案化以在第一电容器电极上形成开口。通过开口蚀刻平面绝缘层，然后形成电容器电介质层。然后在电容器电介质层上形成与第一电容器电极对准的第二电容器电极。将该结构平坦化以暴露平面绝缘层。在优选实施例中，第二电容器电极中的沟槽在平坦化期间通过在平坦化之后剥离的旋涂光致抗蚀剂被保护。

10. 发明授权

US6046472A Graded LDD implant process for sub-half-micron MOS devices 失效
公开(公告)号：US6046472A
公开(公告)日：2000-04-04
申请号：US949997
申请日：1997-10-14
申请人： Aftab Ahmad , Charles Dennison
发明人： Aftab Ahmad , Charles Dennison
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/784
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/823814 , H01L29/1083 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , Y10S257/90 , Y10S257/917
摘要： A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式