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1. 发明授权

US07984204B2 Programmable direct memory access controller having pipelined and sequentially connected stages 有权
标题翻译：可编程直接存储器访问控制器，具有流水线和顺序连接的级
公开(公告)号：US07984204B2
公开(公告)日：2011-07-19
申请号：US12119924
申请日：2008-05-13
申请人： Adrian S. Butter , Liang Chen , Liang Ge
发明人： Adrian S. Butter , Liang Chen , Liang Ge
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.
摘要翻译：直接存储器访问控制器通过系统总线控制对数据处理系统中的存储器的访问。控制器由配置为用数据执行加载操作的数据加载单元组成。数据计算单元被配置为执行数据转换，并且被顺序连接到数据加载单元。数据存储单元也被顺序地连接到数据计算单元，并且被配置为在系统总线上执行突发存储操作以存储在系统存储器中。

2. 发明申请

US20090287860A1 Programmable Direct Memory Access Controller 有权
标题翻译：可编程直接存储器存取控制器
公开(公告)号：US20090287860A1
公开(公告)日：2009-11-19
申请号：US12119924
申请日：2008-05-13
申请人： Adrian S. Butter , Liang Chen , Liang Ge
发明人： Adrian S. Butter , Liang Chen , Liang Ge
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.
摘要翻译：直接存储器访问控制器通过系统总线控制对数据处理系统中的存储器的访问。控制器由配置为用数据执行加载操作的数据加载单元组成。数据计算单元被配置为执行数据转换，并且被顺序连接到数据加载单元。数据存储单元也被顺序地连接到数据计算单元，并且被配置为在系统总线上执行突发存储操作以存储在系统存储器中。

3. 发明授权

US5432848A DES encryption and decryption unit with error checking 失效
标题翻译： DES加密和解密单元进行错误检查
公开(公告)号：US5432848A
公开(公告)日：1995-07-11
申请号：US228474
申请日：1994-04-15
申请人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
发明人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
IPC分类号： H04L9/06 , H04K1/00
CPC分类号： H04L9/0625 , H04L2209/12 , H04L2209/34
摘要： An improved DES unit internally checks whether the DES algorithm is being performed without error. A standard DES algorithm performs an initial permutation of input data and then multiple rounds or iterations of the following: expanding part of a result of the initial permutation for the first iteration and a result of the previous iteration for the subsequent iterations, exclusive ORing a result of the expansion with key bits, performing a selection function on a result of the exclusive ORing, permuting a result of the selection function, and exclusive ORing a result of the permuting. In the improved DES unit, data check bits that correspond to the input data which has been expanded are exclusive NORed with key check bits that correspond to the key, and a result of the exclusive NORing is checked against a result of the exclusive ORing to identify any errors in the operation of the basic DES unit. Also, a check selection function is performed on the result of the exclusive ORing. A result of the check selection function is exclusive NORed with data check bits for another part of the input data to yield input data for input to the expanding function for a next iteration. Also, the improved DES unit checks for accuracy in processing an input key by permuted choicing the input key, key shifting a result of the permuted choicing, and checking a result of the key shifting against key check bits which correspond to the input key and bypass the permuted choicing and key shifting functions.
摘要翻译：改进的DES单元内部检查是否正在执行DES算法而没有错误。标准DES算法执行输入数据的初始置换，然后执行以下的多次或多次迭代：扩展第一次迭代的初始置换结果的一部分和后续迭代的先前迭代的结果，将结果异或使用关键位进行扩展，对异或运算的结果执行选择功能，对选择功能的结果进行置换，并对排列结果进行异或运算。在改进的DES单元中，对应于已经扩展的输入数据的数据校验位与对应于该键的密钥校验位是异或，并且针对异或运算的结果来检查异或的结果以识别基本的DES单元的运行中的任何错误。此外，对异或运算的结果执行检查选择功能。检查选择功能的结果是异或运算，数据校验位用于输入数据的另一部分，以产生用于下一次迭代的扩展功能输入的输入数据。此外，改进的DES单元通过对输入键进行置换来选择输入键的精度来检查输入键的精度，键移动置换的选择的结果，以及检查与对应于输入键和旁路的键检查位的键移位的结果重置的选择和键移动功能。

4. 发明授权

US5566178A Method and system for improving the performance of a token ring network 失效
标题翻译：提高令牌环网络性能的方法和系统
公开(公告)号：US5566178A
公开(公告)日：1996-10-15
申请号：US363425
申请日：1994-12-22
申请人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
发明人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： A system and method for implementing a new protocol that uses new data structures in order to improve the performance of a token ring without changing its topology or degrading its fairness. A primary sender sends a data frame containing a data field addressed to a primary receiver. The protocol allows the primary receiver to enter "transmit mode" and assume another role as a secondary sender when the data frame is received and copied. The secondary sender overwrites the data field. Then, the secondary sender designates a secondary receiver to receive the update data and sends an acknowledgement message back to the primary sender to indicate that it has received data. The secondary receiver sends an acknowledgement to the secondary sender when the secondary transmission data is received. The primary sender checks for an acknowledgement from the primary receiver when the data frame returns. Then the primary sender transmits the data frame downstream. The primary sender regenerates a token and either releases it or seizes it based on whether it has more data to send. The secondary sender verifies the acknowledgement from the secondary receiver and returns to "listen mode".
摘要翻译：一种用于实现使用新数据结构的新协议的系统和方法，以便在不改变其拓扑或降低其公平性的情况下提高令牌环的性能。主发送方发送包含寻址到主接收机的数据字段的数据帧。该协议允许主接收机进入“发送模式”，并在接收和复制数据帧时承担另一个作为次要发送方的角色。辅助发送方覆盖数据字段。然后，辅助发送方指定接收更新数据的辅助接收器，并将确认消息发送回主发送方以指示其已经接收到数据。当接收到辅助传输数据时，辅助接收机向次要发送者发送确认。当数据帧返回时，主发送方检查主接收方的确认。然后主发送方将数据帧发送到下游。主发送方重新生成一个令牌，并根据是否有更多的数据发送，释放它或占用它。辅助发送者验证来自辅助接收机的确认并返回到“监听模式”。

5. 发明授权

US5381480A System for translating encrypted data 失效
标题翻译：用于翻译加密数据的系统
公开(公告)号：US5381480A
公开(公告)日：1995-01-10
申请号：US124151
申请日：1993-09-20
申请人： Adrian S. Butter , Brian S. Finkel , Chang-Yung Kao , Sivarama K. Kodukula , James P. Kuruts
发明人： Adrian S. Butter , Brian S. Finkel , Chang-Yung Kao , Sivarama K. Kodukula , James P. Kuruts
IPC分类号： H04L9/06 , H04L9/16
CPC分类号： H04L9/0625 , H04L2209/125 , H04L2209/24
摘要： A system translates a first group of cipher blocks based on a first encryption key to a second group of respective cipher blocks based on a second encryption key. Respective cipher blocks of the first and second groups represent the same data. The system comprises decryption hardware for sequentially decrypting the cipher blocks of the first group based on the first key. Encryption hardware is coupled to receive decrypted blocks output from the decryption hardware and sequentially encrypts the decrypted blocks into respective cipher blocks of the second group based on the second encryption key. A control unit controls the encryption hardware to encrypt the decrypted blocks into the respective cipher blocks of the second group while the decryption hardware decrypts cipher blocks of the first group. Consequently, decryption and encryption operations occur in parallel and the translation process is expedited.
摘要翻译：系统基于第二加密密钥将基于第一加密密钥的第一组密码块转换为第二组相应加密块。第一组和第二组的各个密码块表示相同的数据。该系统包括用于基于第一密钥顺序地解密第一组的密码块的解密硬件。加密硬件被耦合以接收从解密硬件输出的解密块，并且基于第二加密密钥将解密的块顺序地加密成第二组的相应加密块。控制单元控制加密硬件将解密块加密成第二组的相应加密块，同时解密硬件解密第一组的加密块。因此，解密和加密操作并行发生，并且加速了翻译过程。

6. 发明申请

US20100005213A1 Access Table Lookup for Bus Bridge 有权
标题翻译：公交桥访问表查找
公开(公告)号：US20100005213A1
公开(公告)日：2010-01-07
申请号：US12166571
申请日：2008-07-02
申请人： Adrian S. Butter , Eric M. Foster , Glenn D. Gilda
发明人： Adrian S. Butter , Eric M. Foster , Glenn D. Gilda
IPC分类号： G06F13/14 , G06F13/36
CPC分类号： G06F13/4031 , G06F12/1483
摘要： Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.
摘要翻译：跨条块路由和访问表地址重映射功能在片上系统的交叉条中组合。以这种方式，在段路由之前可能发生地址重映射。每个主端口可能包含一个或多个访问表缓存寄存器。高速缓存寄存器可以允许快速查找与每个主机相关联的一个或多个访问表条目，并且允许多个主机同时查找而不向接入表添加端口。段标识符可以存储在高速缓存寄存器中，以指示如何将匹配请求路由到适当的从段。

7. 发明申请

US20090096481A1 SCHEDULER DESIGN TO OPTIMIZE SYSTEM PERFORMANCE USING CONFIGURABLE ACCELERATION ENGINES 有权
标题翻译：调度器设计，以优化使用配置加速发动机的系统性能
公开(公告)号：US20090096481A1
公开(公告)日：2009-04-16
申请号：US11869823
申请日：2007-10-10
申请人： Adrian S. Butter
发明人： Adrian S. Butter
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware control structure comprises a digital logic circuit design developed to receive configuration data from the hardware acceleration engine describing a selected configuration alternative. The selected configuration alternative is any one of the plurality of configuration alternatives. The digital logic circuit design is developed to process the configuration data to provide an evaluation of an input-to-output latency and an input blocking pattern of the hardware acceleration engine configured according to the selected configuration alternative. The evaluation is capable of being leveraged by control logic within the electronic integrated circuit design to increase utilization of the hardware acceleration engine.
摘要翻译：提供了一种用于硬件加速引擎的可重复使用的硬件控制结构，所述硬件加速引擎可以被配置为在根据多个配置备选方案中的任何一个的电子集成电路设计中实现。可重复使用的硬件控制结构包括数字逻辑电路设计，其开发用于从硬件加速引擎接收描述所选择的配置备选方案的配置数据。所选择的配置替代方案是多个配置替代方案中的任何一个。开发数字逻辑电路设计来处理配置数据以提供根据所选配置替代方案配置的硬件加速引擎的输入到输出延迟和输入阻塞模式的评估。该评估能够由电子集成电路设计中的控制逻辑来利用，以增加硬件加速引擎的利用率。

8. 发明授权

US5528594A Method and system for implementing sub-tokens on a token ring network 失效
标题翻译：在令牌环网上实施子令牌的方法和系统
公开(公告)号：US5528594A
公开(公告)日：1996-06-18
申请号：US363432
申请日：1994-12-22
申请人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
发明人： Adrian S. Butter , Chang Y. Kao , James P. Kuruts
IPC分类号： H04L12/433 , H04L12/427
CPC分类号： H04L12/433
摘要： A method and system for increasing performance on a standard dual ring token ring by generating one or more sub-tokens so that multiple data transmissions can occur concurrently. Upon receipt of a data frame from the token holder, interface logic enables a receiver to generate a sub-token frame. The sub-token is used to notify the next downstream station that it may transmit data frames to other downstream stations. In this way, a second data transmission path can be established between downstream stations. In a similar manner, the receiver of a data frame sent by a sub-token owner will generate a sub-token frame for use by the next downstream station when its data arrives. Each sub-token is used to create a new sub-ring, thus allowing for concurrent data transmissions. Each new sub-ring must obey token ring protocol to avoid data collisions.
摘要翻译：一种用于通过生成一个或多个子令牌来提高标准双环令牌环的性能以便多个数据传输可以同时发生的方法和系统。接口逻辑在从令牌持有者接收到数据帧时，使得接收器能够生成子令牌帧。子令牌用于通知下一个下游站它可以向其他下游站传输数据帧。以这种方式，可以在下游站之间建立第二数据传输路径。以类似的方式，由子令牌所有者发送的数据帧的接收者将产生一个子令牌帧，以供下一个下游站在其数据到达时使用。每个子令牌用于创建新的子环，从而允许并发数据传输。每个新的子环必须遵守令牌环协议以避免数据冲突。

9. 发明授权

US07752592B2 Scheduler design to optimize system performance using configurable acceleration engines 有权
标题翻译：调度器设计，使用可配置的加速引擎优化系统性能
公开(公告)号：US07752592B2
公开(公告)日：2010-07-06
申请号：US11869823
申请日：2007-10-10
申请人： Adrian S. Butter
发明人： Adrian S. Butter
IPC分类号： G06F17/50 , G06F9/00 , G06F15/177 , H03K19/177
CPC分类号： G06F17/5054
摘要： A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware control structure comprises a digital logic circuit design developed to receive configuration data from the hardware acceleration engine describing a selected configuration alternative. The selected configuration alternative is any one of the plurality of configuration alternatives. The digital logic circuit design is developed to process the configuration data to provide an evaluation of an input-to-output latency and an input blocking pattern of the hardware acceleration engine configured according to the selected configuration alternative. The evaluation is capable of being leveraged by control logic within the electronic integrated circuit design to increase utilization of the hardware acceleration engine.
摘要翻译：提供了一种用于硬件加速引擎的可重复使用的硬件控制结构，所述硬件加速引擎可以被配置为在根据多个配置备选方案中的任何一个的电子集成电路设计中实现。可重复使用的硬件控制结构包括数字逻辑电路设计，其开发用于从硬件加速引擎接收描述所选择的配置备选方案的配置数据。所选择的配置替代方案是多个配置替代方案中的任何一个。开发数字逻辑电路设计来处理配置数据以提供根据所选配置替代方案配置的硬件加速引擎的输入到输出延迟和输入阻塞模式的评估。该评估能够由电子集成电路设计中的控制逻辑来利用，以增加硬件加速引擎的利用率。

10. 发明授权

US6097757A Real-time variable bit rate encoding of video sequence employing statistics 失效
标题翻译：使用图像统计的视频序列的实时可变比特率编码
公开(公告)号：US6097757A
公开(公告)日：2000-08-01
申请号：US8282
申请日：1998-01-16
申请人： Charles E. Boice , Adrian S. Butter , Agnes Y. Ngai , Nader Mohsenian , Robert Woodard
发明人： Charles E. Boice , Adrian S. Butter , Agnes Y. Ngai , Nader Mohsenian , Robert Woodard
IPC分类号： H04N7/36 , H04N7/50
CPC分类号： H04N19/182 , H04N19/107 , H04N19/114 , H04N19/124 , H04N19/137 , H04N19/14 , H04N19/149 , H04N19/162 , H04N19/172 , H04N19/186 , H04N19/51 , H04N19/61
摘要： Method, system and computer program product are provided for adaptively encoding in hardware, software or a combination thereof a sequence of video frames in real-time. Pre-encode perceptual activity measurement processing is employed to derive statistics on each frame of the sequence of video frames to be encoded. The statistics are used by variable bit rate logic to obtain a number of bits to be used in encoding each frame. The number of bits to be used is provided to a single encoding engine, which encodes the sequence of video frames and produces a constant quality, variable bit rate bitstream output. The pre-encode processing employs a regulator as the global data flow control and synchronization for the encoder. Perceptual activity analysis on each frame of the sequence of video frames can derive information on, for example, shading, scene change, fade, color, motion and/or edge presence within the frame. Voting gives greater weight to the presence of certain characteristics within the frame.
摘要翻译：提供方法，系统和计算机程序产品，用于在硬件，软件或其组合中自动编码一系列视频帧。采用预编码感知活动测量处理来导出要编码的视频帧序列的每个帧的统计。统计量由可变比特率逻辑用于获得要用于编码每个帧的位数。要使用的比特数被提供给单个编码引擎，其编码视频帧序列并产生恒定质量的可变比特率比特流输出。预编码处理采用调节器作为编码器的全局数据流控制和同步。对视频帧序列的每个帧的感知活动分析可以得到关于帧内的阴影，场景变化，褪色，颜色，运动和/或边缘存在的信息。表决给予框架内存在某些特征的更大的权重。

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