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1. 发明授权

US06414539B1 AC timings at the input buffer of source synchronous and common clock designs by making the supply for differential amplifier track the reference voltage 有权
标题翻译：通过使差分放大器的电源跟踪参考电压，在源同步和公共时钟设计的输入缓冲器处的交流定时
公开(公告)号：US06414539B1
公开(公告)日：2002-07-02
申请号：US09819717
申请日：2001-03-29
申请人： Adhiveeraraghavan Srikanth , Navneet Dour
发明人： Adhiveeraraghavan Srikanth , Navneet Dour
IPC分类号： G05F110
CPC分类号： G05F1/46
摘要： A differential amplifier power supply is derived from the same source that generates the reference voltage for the differential amplifiers. This will ensure the direction of voltage level shifts of these two voltages to be in tandem. That is, these two voltages will move in the same direction due to any variations in the source since they are generated from the same regulator. In this way receiver timing errors can be significantly reduced in source synchronous and common clock interfaces.
摘要翻译：差分放大器电源源自产生差分放大器的参考电压的相同源。这将确保这两个电压的电压电平偏移方向一致。也就是说，这两个电压由于源自相同调节器的任何变化而在相同的方向上移动。以这种方式，在源同步和公共时钟接口中，接收机定时误差可以大大降低。

2. 发明授权

US07012451B2 Slew rate at buffers by isolating predriver from driver 失效
公开(公告)号：US07012451B2
公开(公告)日：2006-03-14
申请号：US10618479
申请日：2003-07-11
申请人： Adhiveeraraghavan Srikanth , Navneet Dour
发明人： Adhiveeraraghavan Srikanth , Navneet Dour
IPC分类号： H03B1/00
CPC分类号： H03K17/162 , H03K17/163
摘要： In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate. The drivers have driver power and ground connections. On-die pre-driver power and ground planes are coupled to the pre-driver power and ground connections on die of the integrated circuit, respectively. On-die driver power and ground planes are coupled to the driver power and ground connections on-die of the integrated circuit, respectively. The driver power and ground planes are separated from the pre-driver power and ground planes on the die, and/or on the package to maintain the desired slew rate.

3. 发明申请

US20050013071A1 Slew rate at buffers by isolating predriver from driver 失效
标题翻译：通过从驱动程序中隔离预驱动器来缓冲缓冲区的速率
公开(公告)号：US20050013071A1
公开(公告)日：2005-01-20
申请号：US10618479
申请日：2003-07-11
申请人： Adhiveeraraghavan Srikanth , Navneet Dour
发明人： Adhiveeraraghavan Srikanth , Navneet Dour
IPC分类号： H03K17/16 , H02H9/08
CPC分类号： H03K17/162 , H03K17/163
摘要： In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate. The drivers have driver power and ground connections. On-die pre-driver power and ground planes are coupled to the pre-driver power and ground connections on die of the integrated circuit, respectively. On-die driver power and ground planes are coupled to the driver power and ground connections on-die of the integrated circuit, respectively. The driver power and ground planes are separated from the pre-driver power and ground planes on the die, and/or on the package to maintain the desired slew rate.
摘要翻译：在一个实施例中，预驱动器基于由控制电路提供的控制信号产生预驱动信号。前驱动器具有预驱动器电源和接地连接。预驱动信号在频带上工作。驱动器基于输出焊盘处的预驱动信号产生输出信号。输出信号具有转换速率。该驱动器具有驱动器电源和接地连接。低通滤波器耦合在预驱动器和驱动器电源和接地连接之间，以减少在预驱动信号处的噪声的影响。低通滤波器具有对应于噪声频率的截止频率。在另一个实施例中，多个预驱动器基于由控制电路提供的控制信号产生预驱动信号。前驱动器具有前驱动器电源和接地连接。多个驱动器基于集成电路的输出焊盘处的预驱动信号产生多个输出信号。每个输出信号具有压摆率。驱动器具有驱动器电源和接地连接。片上预驱动器电源和接地层分别耦合到集成电路管芯上的预驱动器电源和接地连接。片上驱动器电源和接地层分别耦合到集成电路的芯片上的驱动器电源和接地连接。驱动器电源和接地层与芯片上的预驱动器电源和接地层以及/或封装分离，以保持所需的转换速率。

4. 发明授权

US06617891B2 Slew rate at buffers by isolating predriver from driver 有权
标题翻译：通过从驱动程序中隔离预驱动器来缓冲缓冲区的速率
公开(公告)号：US06617891B2
公开(公告)日：2003-09-09
申请号：US09965110
申请日：2001-09-26
申请人： Adhiveeraraghavan Srikanth , Navneet Dour
发明人： Adhiveeraraghavan Srikanth , Navneet Dour
IPC分类号： H03B100
CPC分类号： H03K17/162 , H03K17/163
摘要： In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate. The drivers have driver power and ground connections. On-die pre-driver power and ground planes are coupled to the pre-driver power and ground connections on die of the integrated circuit, respectively. On-die driver power and ground planes are coupled to the driver power and ground connections on-die of the integrated circuit, respectively. The driver power and ground planes are separated from the pre-driver power and ground planes on the die, and/or on the package to maintain the desired slew rate.
摘要翻译：在一个实施例中，预驱动器基于由控制电路提供的控制信号产生预驱动信号。前驱动器具有预驱动器电源和接地连接。预驱动信号在频带上工作。驱动器基于输出焊盘处的预驱动信号产生输出信号。输出信号具有转换速率。该驱动器具有驱动器电源和接地连接。低通滤波器耦合在预驱动器和驱动器电源和接地连接之间，以减少在预驱动信号处的噪声的影响。低通滤波器具有对应于噪声频率的截止频率。在另一个实施例中，多个预驱动器基于由控制电路提供的控制信号产生预驱动信号。前驱动器具有前驱动器电源和接地连接。多个驱动器基于集成电路的输出焊盘处的预驱动信号产生多个输出信号。每个输出信号具有压摆率。驱动器具有驱动器电源和接地连接。片上预驱动器电源和接地层分别耦合到集成电路管芯上的预驱动器电源和接地连接。片上驱动器电源和接地层分别耦合到集成电路的芯片上的驱动器电源和接地连接。驱动器电源和接地层与芯片上的预驱动器电源和接地层以及/或封装分离，以保持所需的转换速率。

5. 发明申请

US20060245473A1 Integrating receivers for source synchronous protocol 审中-公开
标题翻译：用于源同步协议的集成接收器
公开(公告)号：US20060245473A1
公开(公告)日：2006-11-02
申请号：US11118227
申请日：2005-04-28
申请人： Roger Cheng , Navneet Dour , Scott Miller , David Freker , Harishankar Sridharan , Mahmood Alam
发明人： Roger Cheng , Navneet Dour , Scott Miller , David Freker , Harishankar Sridharan , Mahmood Alam
IPC分类号： H04B1/00
CPC分类号： G06F13/423 , Y02D10/14 , Y02D10/151
摘要： An embodiment of the present invention is a technique to integrate data for a source synchronous protocol. A delay generator generates at least an integrating strobe from a data strobe synchronizing a data having a data window using the source synchronous protocol. A pulse generator generates a pulse from the at least integrating strobe. An integrating receiver integrates the data over an integration window defined by the pulse. The integration window is within the data window.
摘要翻译：本发明的一个实施例是用于集成源同步协议的数据的技术。延迟发生器使用源同步协议从数据选通器产生至少一个使具有数据窗口的数据同步的积分选通脉冲。脉冲发生器从至少积分选通脉冲产生脉冲。积分接收器通过由脉冲定义的积分窗口来集成数据。集成窗口在数据窗口内。

6. 发明申请

US20060119381A1 PVT controller for programmable on die termination 有权
标题翻译： PVT控制器，用于可编程芯片端接
公开(公告)号：US20060119381A1
公开(公告)日：2006-06-08
申请号：US11337131
申请日：2006-01-19
申请人： Navneet Dour , Roger Cheng
发明人： Navneet Dour , Roger Cheng
IPC分类号： H03K19/003
CPC分类号： H03K19/018521 , H03K19/00384 , H03K19/018585
摘要： Embodiments include an on die termination circuit. The on die termination circuit may be programmable. The on die termination circuit may be programmed to compensate for environmental conditions and the physical characteristics of the device. The programmed on die termination circuit allows for faster transfer rates over communication lines by reducing the time needed to recover from signal reflection and similar issues.
摘要翻译：实施例包括芯片上终端电路。芯片终端电路可以是可编程的。芯片终端电路可以被编程以补偿环境条件和设备的物理特性。通过减少从信号反射恢复所需的时间和类似的问题，编程的芯片终端电路允许通信线路上的传输速率更快。

7. 发明授权

US07746135B2 Wake-up circuit 有权
标题翻译：唤醒电路
公开(公告)号：US07746135B2
公开(公告)日：2010-06-29
申请号：US11864923
申请日：2007-09-29
申请人： Jacob S. Schneider , Navneet Dour , Harishankar Sridharan
发明人： Jacob S. Schneider , Navneet Dour , Harishankar Sridharan
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0802 , H03L7/0805 , H03L7/0812 , H03L7/10
摘要： Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be “awoken” (brought up to a control bias level) in a sufficiently small enough amount of time. The wake-up circuit couples a bias input node to a voltage level that is higher then the control bias level in response to a wake-up event, and then it couples the control bias node to the bias input node in response to their voltage levels being sufficiently close to one another.
摘要翻译：这里公开了一种用于诸如从属DLL电路的电路的偏置输入的唤醒电路，以允许其被放置在降低功率模式中并且被充分地“唤醒”（提高到控制偏置电平）足够小的时间。唤醒电路将偏置输入节点耦合到响应于唤醒事件的高于控制偏置电平的电压电平，然后响应于其电压电平将控制偏置节点耦合到偏置输入节点充分接近彼此。

8. 发明申请

US20070007992A1 Method to calibrate DRAM Ron and ODT values over PVT 有权
标题翻译：通过PVT校准DRAM Ron和ODT值的方法
公开(公告)号：US20070007992A1
公开(公告)日：2007-01-11
申请号：US11174009
申请日：2005-06-30
申请人： Kuljit Bains , Navneet Dour , Hany Fahmy , George Vergis , Christopher Cox
发明人： Kuljit Bains , Navneet Dour , Hany Fahmy , George Vergis , Christopher Cox
IPC分类号： H03K19/003
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254 , H04L25/0298
摘要： An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.
摘要翻译：实施例可以包括具有存储器阵列的存储器，耦合到参考电压的电阻器，与电阻器耦合的管芯端接电路上，以及耦合到管芯端接电路并与存储器阵列耦合的输入端，用于接收校准命令停止使用输入和存储器阵列，并用耦合到参考电压的电阻校准芯片上的端接电路。本文公开了其它实施例。

9. 发明申请

US20060114742A1 Method and apparatus for optimizing strobe to clock relationship 有权
标题翻译：用于优化频闪到时钟关系的方法和装置
公开(公告)号：US20060114742A1
公开(公告)日：2006-06-01
申请号：US11001554
申请日：2004-11-30
申请人： Joe Salmon , Navneet Dour , George Vergis
发明人： Joe Salmon , Navneet Dour , George Vergis
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.
摘要翻译：为了允许存储器控制器将选通脉冲与DRAM的时钟关系同步，诸如触发器的寄存器被并入DRAM内以便于利用DQS对SCLK进行采样。同样，当DRAM处于测试操作模式时，存储器控制器将时钟提前或延迟到存储器控制器集线器（MCH）处的DQS以实现适当的DRAM关系。在一个实施例中，如果读取二进制零值，则存储器控制器提前DQS。相比之下，如果读取二进制一个值，则内存控制器会阻止DQS。

10. 发明授权

US07432731B2 Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations 有权
标题翻译：在过程，电压和温度（PVT）变化上校准DRAM电阻（Ron）和芯片上终端（ODT）值的方法和装置
公开(公告)号：US07432731B2
公开(公告)日：2008-10-07
申请号：US11174009
申请日：2005-06-30
申请人： Kuljit S. Bains , Navneet Dour , Hany Fahmy , George Vergis , Christopher E. Cox
发明人： Kuljit S. Bains , Navneet Dour , Hany Fahmy , George Vergis , Christopher E. Cox
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254 , H04L25/0298
摘要： An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.
摘要翻译：实施例可以包括具有存储器阵列的存储器，耦合到参考电压的电阻器，与电阻器耦合的管芯端接电路上，以及耦合到管芯端接电路并与存储器阵列耦合的输入端，用于接收校准命令停止使用输入和存储器阵列，并用耦合到参考电压的电阻校准芯片上的端接电路。本文公开了其它实施例。

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