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1. 发明授权

US07369634B2 Training pattern for a biased clock recovery tracking loop 有权
标题翻译：有针对性的时钟恢复跟踪循环的训练模式
公开(公告)号：US07369634B2
公开(公告)日：2008-05-06
申请号：US10935903
申请日：2004-09-07
申请人： Adarsh Panikkar , Kersi H. Vakil , Pete D. Vogt
发明人： Adarsh Panikkar , Kersi H. Vakil , Pete D. Vogt
IPC分类号： H04L7/00
CPC分类号： H04L7/041 , H04L7/044 , H04L7/046
摘要： Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.
摘要翻译：本发明的一些实施例提供可包括编码信息的偏置跟踪环路。实施例可以包括以允许时钟恢复，嵌入式信息传输和/或头部对准的非干扰方式使用的训练模式。因此，实施例可以包括包括数据的跟踪环路训练模式。

2. 发明授权

US08098783B2 Training pattern for a biased clock recovery tracking loop 有权
标题翻译：有针对性的时钟恢复跟踪循环的训练模式
公开(公告)号：US08098783B2
公开(公告)日：2012-01-17
申请号：US12111106
申请日：2008-04-28
申请人： Adarsh Panikkar , Kersi H. Vakil , Pete D. Vogt
发明人： Adarsh Panikkar , Kersi H. Vakil , Pete D. Vogt
IPC分类号： H04L7/00
CPC分类号： H04L7/041 , H04L7/044 , H04L7/046
摘要： Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.
摘要翻译：本发明的一些实施例提供可包括编码信息的偏置跟踪环路。实施例可以包括以允许时钟恢复，嵌入式信息传输和/或头部对准的非干扰方式使用的训练模式。因此，实施例可以包括包括数据的跟踪环路训练模式。

3. 发明申请

US20080260082A1 TRAINING PATTERN FOR A BIASED CLOCK RECOVERY TRACKING LOOP 有权
标题翻译：用于偏心时钟追踪追踪的训练模式
公开(公告)号：US20080260082A1
公开(公告)日：2008-10-23
申请号：US12111106
申请日：2008-04-28
申请人： Adarsh Panikkar , Kersi H. Vakil , Pete D. Vogt
发明人： Adarsh Panikkar , Kersi H. Vakil , Pete D. Vogt
IPC分类号： H04L7/00
CPC分类号： H04L7/041 , H04L7/044 , H04L7/046
摘要： Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alignment. Therefore, embodiments may comprise a tracking loop training pattern that comprises data.
摘要翻译：本发明的一些实施例提供可包括编码信息的偏置跟踪环路。实施例可以包括以允许时钟恢复，嵌入式信息传输和/或头部对准的非干扰方式使用的训练模式。因此，实施例可以包括包括数据的跟踪环路训练模式。

4. 发明授权

US09841920B2 Heterogeneous memory die stacking for energy efficient computing 有权
公开(公告)号：US09841920B2
公开(公告)日：2017-12-12
申请号：US13997241
申请日：2011-12-29
申请人： Pete D. Vogt
发明人： Pete D. Vogt
IPC分类号： G06F13/38 , G06F3/06 , G11C5/02 , G11C5/06
CPC分类号： G06F3/0647 , G06F3/0604 , G06F3/0683 , G06F2003/0697 , G11C5/025 , G11C5/063
摘要： Methods and apparatus to provide heterogeneous memory die stacking for energy efficient computing are described. In one embodiment, a Phase Change Memory with Switch (PCMS) die is coupled to a Dynamic Random Access Memory (DRAM) die and a Central Processing Unit (CPU) die. CPU checkpointing state data is stored in the PCMS die first before transferring the checkpointing data to a backup media at a later and more extended time. Other embodiments are also disclosed and claimed.

5. 发明授权

US08843794B2 Method, system and apparatus for evaluation of input/output buffer circuitry 有权
标题翻译：用于评估输入/输出缓冲电路的方法，系统和装置
公开(公告)号：US08843794B2
公开(公告)日：2014-09-23
申请号：US13625744
申请日：2012-09-24
申请人： Christopher J. Nelson , Tak M. Mak , David J. Zimmerman , Pete D. Vogt
发明人： Christopher J. Nelson , Tak M. Mak , David J. Zimmerman , Pete D. Vogt
IPC分类号： G01R31/28 , G06F11/00 , G06F13/42 , G01R31/00 , G06F13/00 , G01R31/317 , G11C29/02 , G01R31/3187 , G06F11/34 , G11C7/10 , G11C29/12 , H04L1/24 , G01R31/3177 , G01R31/3181 , G11C29/32
CPC分类号： G01R31/31716 , G01R31/31713 , G01R31/3177 , G01R31/3181 , G01R31/3187 , G06F11/3485 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/32 , H04L1/243
摘要： Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
摘要翻译：用于评估I / O缓冲电路的技术和机制。在一个实施例中，对包括I / O缓冲器电路的设备执行测试轮，每个测试轮包括对于每个I / O缓冲器电路的相应回环测试。每个测试轮对应于发送时钟信号和接收时钟信号之间的不同的相应延迟。在另一个实施例中，第一测试轮指示至少一个I / O缓冲器电路的故障条件，第二测试轮指示每个I / O缓冲电路的故障条件。 I / O缓冲电路的评估确定装置是否满足测试条件，其中确定是基于与第一测试轮对应的延迟与对应于第二测试轮的延迟之间的差。

6. 发明申请

US20140089752A1 METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER CIRCUITRY 有权
标题翻译：用于评估输入/输出缓冲器电路的方法，系统和装置
公开(公告)号：US20140089752A1
公开(公告)日：2014-03-27
申请号：US13625744
申请日：2012-09-24
申请人： Christopher J. Nelson , Tak M. Mak , David J. Zimmerman , Pete D. Vogt
发明人： Christopher J. Nelson , Tak M. Mak , David J. Zimmerman , Pete D. Vogt
IPC分类号： G01R31/3177
CPC分类号： G01R31/31716 , G01R31/31713 , G01R31/3177 , G01R31/3181 , G01R31/3187 , G06F11/3485 , G11C7/10 , G11C29/02 , G11C29/022 , G11C29/1201 , G11C29/32 , H04L1/243
摘要： Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a respective loop-back test for each of the I/O buffer circuits. Each of the test rounds corresponds to a different respective delay between a transmit clock signal and a receive clock signal. In another embodiment, a first test round indicates a failure condition for at least one I/O buffer circuit and a second test round indicates the failure condition for each of the I/O buffer circuits. Evaluation of the I/O buffer circuits determines whether the device satisfies a test condition, where the determining is based on a difference between the delay corresponding to the first test round and the delay corresponding to the second test round.
摘要翻译：用于评估I / O缓冲电路的技术和机制。在一个实施例中，对包括I / O缓冲器电路的设备执行测试轮，每个测试轮包括对于每个I / O缓冲器电路的相应回环测试。每个测试轮对应于发送时钟信号和接收时钟信号之间的不同的相应延迟。在另一个实施例中，第一测试轮指示至少一个I / O缓冲器电路的故障条件，第二测试轮指示每个I / O缓冲电路的故障条件。 I / O缓冲电路的评估确定装置是否满足测试条件，其中确定是基于与第一测试轮对应的延迟与对应于第二测试轮的延迟之间的差。

7. 发明授权

US08286039B2 Disabling outbound drivers for a last memory buffer on a memory channel 失效
公开(公告)号：US08286039B2
公开(公告)日：2012-10-09
申请号：US13340552
申请日：2011-12-29
申请人： Pete D. Vogt , Dennis W. Brzezinski , Warren R. Morrow
发明人： Pete D. Vogt , Dennis W. Brzezinski , Warren R. Morrow
IPC分类号： G01R31/28
CPC分类号： G06F12/00 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

8. 发明授权

US07702874B2 Memory device identification 有权
标题翻译：存储设备识别
公开(公告)号：US07702874B2
公开(公告)日：2010-04-20
申请号：US11165595
申请日：2005-06-22
申请人： Pete D. Vogt
发明人： Pete D. Vogt
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C11/4072 , G11C7/20 , H01L2924/15174 , H01L2924/15311
摘要： A memory device may determine its device ID in response to the order of a received training pattern. The training pattern may be transmitted over swizzled signal lines to multiple memory devices arranged in a logical stack. Each memory device may be packaged on a substrate having the swizzled signal lines. The memory devices may be physically stacked or planar. Other embodiments are described and claimed.
摘要翻译：存储器设备可以响应于所接收的训练模式的顺序来确定其设备ID。训练模式可以通过交错的信号线发送到布置在逻辑堆栈中的多个存储器件。每个存储器件可以封装在具有变化的信号线的衬底上。存储器件可以物理堆叠或平面。描述和要求保护其他实施例。

9. 发明授权

US07417883B2 I/O data interconnect reuse as repeater 有权
标题翻译： I / O数据互连重用为中继器
公开(公告)号：US07417883B2
公开(公告)日：2008-08-26
申请号：US11027004
申请日：2004-12-30
申请人： Pete D. Vogt
发明人： Pete D. Vogt
IPC分类号： G11C5/06
CPC分类号： G11C5/04
摘要： Some embodiments may include a memory with a first memory device and data pins, and a second memory device coupled with some of the data pins of the first memory device, allowing the first memory device to operate as a data repeater for the second memory device. An embodiment may comprise a memory device with a memory die, a first plurality of data pins to operate as input and output to the memory die, and a second plurality of data pins to function as a repeater. An embodiment method may involve configuring a first memory device as a repeater, sending data to the first memory device, and forwarding the data to a second memory device.
摘要翻译：一些实施例可以包括具有第一存储器设备和数据引脚的存储器，以及与第一存储器设备的一些数据引脚耦合的第二存储器件，允许第一存储器件作为第二存储器件的数据中继器工作。实施例可以包括具有存储器管芯的存储器件，用作作为输入和输出到存储管芯的第一多个数据管脚和用作中继器的第二多个数据管脚。实施例方法可以包括将第一存储器设备配置为中继器，向第一存储器设备发送数据，以及将数据转发到第二存储器设备。

10. 发明授权

US07366931B2 Memory modules that receive clock information and are placed in a low power state 有权
标题翻译：接收时钟信息并置于低功率状态的内存模块
公开(公告)号：US07366931B2
公开(公告)日：2008-04-29
申请号：US11027237
申请日：2004-12-30
申请人： Pete D. Vogt
发明人： Pete D. Vogt
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G11C5/14 , G06F2213/0038 , G11C5/04 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Embodiments described herein provide a power saving state for a memory system. For example, a memory system may derive clocking information from a training pattern sent over a memory channel. A memory may comprise a link to receive training frames, and circuitry to derive a clock from the training frames, and place the memory module in a low power state between training frames. Embodiments as described herein may utilize periodic training frames to implement a power saving state on the channel or the memory system, either in whole or in part.
摘要翻译：本文描述的实施例提供了用于存储器系统的省电状态。例如，存储器系统可以从通过存储器通道发送的训练模式导出时钟信息。存储器可以包括用于接收训练帧的链路，以及从训练帧导出时钟的电路，并且将训练帧之间的存储器模块置于低功率状态。本文描述的实施例可以利用周期性训练帧来实现在信道或存储器系统上的全部或部分的省电状态。

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