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    • 1. 发明申请
    • METHODS OF FOMRING ARRAY OF NANOSCOPIC MOSFET TRANSISTORS
    • NANOSCOPIC MOSFET晶体管阵列的方法
    • US20110159648A1
    • 2011-06-30
    • US13040401
    • 2011-03-04
    • Adam L. GhozeilJames StasiakKevin PetersGalen H. Kawamoto
    • Adam L. GhozeilJames StasiakKevin PetersGalen H. Kawamoto
    • H01L21/336
    • H01L29/66825H01L21/28273H01L21/823437H01L29/1033H01L29/66575
    • A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.
    • 纳米晶体管通过在半导体衬底上形成氧化物层,施加抗蚀剂,使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案,在图案上施加第一离子掩模材料,选择性地将其提升到 留下第一离子掩模以形成栅极,通过注入合适的掺杂剂形成掺杂区域,施加另一层抗蚀剂并使用压印光刻图案化第二抗蚀剂层以形成沿着第二方向排列的第二图案,施加第二离子掩模 材料选择性地将其提起以留下由第二图案限定的第二离子掩模,以及通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域。 该方法可用于制造纳米晶体管阵列。
    • 2. 发明授权
    • Methods of fomring array of nanoscopic MOSFET transistors
    • 制造纳米级MOSFET晶体管阵列的方法
    • US08329527B2
    • 2012-12-11
    • US13040401
    • 2011-03-04
    • Adam L GhozeilJames StasiakKevin PetersGalen H. Kawamoto
    • Adam L GhozeilJames StasiakKevin PetersGalen H. Kawamoto
    • H01L21/336
    • H01L29/66825H01L21/28273H01L21/823437H01L29/1033H01L29/66575
    • A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.
    • 纳米晶体管通过在半导体衬底上形成氧化物层,施加抗蚀剂,使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案,在图案上施加第一离子掩模材料,选择性地将其提升到 留下第一离子掩模以形成栅极,通过注入合适的掺杂剂形成掺杂区域,施加另一层抗蚀剂并使用压印光刻图案化第二抗蚀剂层以形成沿着第二方向排列的第二图案,施加第二离子掩模 材料选择性地将其提起以留下由第二图案限定的第二离子掩模,以及通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域。 该方法可用于制造纳米晶体管阵列。
    • 3. 发明授权
    • Array of nanoscopic MOSFET transistors and fabrication methods
    • 纳米MOSFET晶体管阵列及其制造方法
    • US07902015B2
    • 2011-03-08
    • US11126710
    • 2005-05-10
    • Adam L GhozeilJames StasiakKevin PetersGalen H. Kawamoto
    • Adam L GhozeilJames StasiakKevin PetersGalen H. Kawamoto
    • H01L21/8238
    • H01L29/66825H01L21/28273H01L21/823437H01L29/1033H01L29/66575
    • A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.
    • 纳米晶体管通过在半导体衬底上形成氧化物层,施加抗蚀剂,使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案,在图案上施加第一离子掩模材料,选择性地将其提升到 留下第一离子掩模以形成栅极,通过注入合适的掺杂剂形成掺杂区域,施加另一层抗蚀剂并使用压印光刻图案化第二抗蚀剂层以形成沿着第二方向排列的第二图案,施加第二离子掩模 材料选择性地将其提起以留下由第二图案限定的第二离子掩模,以及通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域。 该方法可用于制造纳米晶体管阵列。
    • 4. 发明授权
    • Array of nanoscopic mosfet transistors and fabrication methods
    • 纳米晶体管阵列和制造方法
    • US07005335B2
    • 2006-02-28
    • US10620858
    • 2003-07-15
    • Adam L GhozeilJames StasiakKevin PetersGalen H. Kawamoto
    • Adam L GhozeilJames StasiakKevin PetersGalen H. Kawamoto
    • H01L21/8238
    • H01L29/66825H01L21/28273H01L21/823437H01L29/1033H01L29/66575
    • A nanoscopic transistor is made by forming an oxide layer on a semiconductor substrate, applying resist, patterning the resist using imprint lithography to form a pattern aligned along a first direction, applying a first ion-masking material over the pattern, selectively lifting it off to leave a first ion mask to form a gate, forming doped regions by implanting a suitable dopant, applying another layer of resist and patterning the second resist layer using imprint lithography to form a second pattern aligned along a second direction, applying a second ion-masking material over the second pattern, selectively lifting it off to leave a second ion mask defined by the second pattern, and forming second doped regions in the substrate by implanting a suitable second dopant selectively in accordance with the second ion mask. The method may be used to make an array of nanoscopic transistors.
    • 纳米晶体管通过在半导体衬底上形成氧化物层,施加抗蚀剂,使用压印光刻对抗蚀剂进行构图以形成沿着第一方向排列的图案,在图案上施加第一离子掩模材料,选择性地将其提升到 留下第一离子掩模以形成栅极,通过注入合适的掺杂剂形成掺杂区域,施加另一层抗蚀剂并使用压印光刻图案化第二抗蚀剂层以形成沿着第二方向排列的第二图案,施加第二离子掩模 材料选择性地将其提起以留下由第二图案限定的第二离子掩模,以及通过根据第二离子掩模选择性地注入合适的第二掺杂剂而在衬底中形成第二掺杂区域。 该方法可用于制造纳米晶体管阵列。