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1. 发明申请

US20060106555A1 Method for using an alternate performance test to reduce test time and improve manufacturing yield 审中-公开
标题翻译：使用替代性能测试来减少测试时间并提高制造产量的方法
公开(公告)号：US20060106555A1
公开(公告)日：2006-05-18
申请号：US11303406
申请日：2005-12-16
申请人： Ram Voorakaranam , Abhijit Chatterjee , Sasikumar Cherubal , David Majernik
发明人： Ram Voorakaranam , Abhijit Chatterjee , Sasikumar Cherubal , David Majernik
IPC分类号： G06F19/00
CPC分类号： G01R31/2831
摘要： A method for using an alternate performance test to reduce test time and improve manufacturing yield. The method comprises establishing a specification test limit within which a product would be accepted under specification test criteria and inner and outer alternate test error bounds relative to the specification test limit; initially testing the product with the alternate test; accepting the product if the alternate test result is within the inner alternate test error bound; rejecting the product if the alternate test result is outside the outer alternate test error bound; and retesting the product using the specification test if the alternate test result is on or between the alternate error bounds. On retesting, the product is ordinarily rejected if the specification test result is outside the specification test limits. The method may further comprise modifying a production test to produce a specification test whose guardband is narrower than the production test. The alternate test may provide a reduction of test time from that required by the specification test, and may be a signature test. The method can be used where the acceptability parameter value distribution for the product is peaked, and the specification test has upper and lower test limits.
摘要翻译：一种使用替代性能测试来减少测试时间并提高制造产量的方法。该方法包括建立规范测试极限，在规范测试标准范围内接受产品，在相对于规范测试极限的情况下，内外替代测试误差范围; 首先用替代测试测试产品; 如果替代测试结果在内部替代测试误差范围内，则接受产品; 如果替代测试结果在外部替代测试误差界限之外，则拒绝产品; 并且如果备用测试结果在备用误差范围之间或之间，则使用规范测试重新测试产品。在重新测试时，如果规格测试结果超出规格测试限制，则产品通常被拒绝。该方法还可以包括修改生产测试以产生其保护带窄于生产测试的规格测试。替代测试可以提供从规范测试所要求的测试时间的减少，并且可以是签名测试。该方法可用于产品可接受参数值分布达到峰值，规格试验具有上限和下限。

2. 发明授权

US06964004B2 Method and apparatus for testing a system-on-a-chip 失效
标题翻译：用于测试片上系统的方法和装置
公开(公告)号：US06964004B2
公开(公告)日：2005-11-08
申请号：US10280543
申请日：2002-10-24
申请人： Abhijit Chatterjee , Dave Majernik , Sasikumar Cherubal , Sudip Chakrabarti , Ramakrishna Voorakaranam , Jacob A. Abraham , Douglas Goodman
发明人： Abhijit Chatterjee , Dave Majernik , Sasikumar Cherubal , Sudip Chakrabarti , Ramakrishna Voorakaranam , Jacob A. Abraham , Douglas Goodman
IPC分类号： G01R31/3167 , G01R31/3185 , G01R31/28
CPC分类号： G01R31/318505 , G01R31/3167
摘要： A method for testing a system on a chip or a system on a package (““SOPC”) having a plurality of internal modules that are tested to determine whether predetermined performance specifications are satisfied. A first module of the SOPC is selected for testing. A determination is made as to whether the first module is directly accessible or not. If the first module is directly accessible, the module may be tested with automated test equipment external to the SOPC. If the first module is not directly accessible, the module may be tested with a second and third module of the SOPC.
摘要翻译：一种用于测试芯片上的系统或者具有多个内部模块的封装上的系统（“SOPC”）的方法，所述多个内部模块被测试以确定是否满足预定的性能规范。选择SOPC的第一模块进行测试。确定第一模块是否可直接访问，如果第一模块可直接访问，则可以使用SOPC外部的自动测试设备对模块进行测试，如果第一模块不可直接访问，则模块可以用SOPC的第二和第三个模块进行测试。

3. 发明授权

US07006939B2 Method and apparatus for low cost signature testing for analog and RF circuits 失效
公开(公告)号：US07006939B2
公开(公告)日：2006-02-28
申请号：US09837887
申请日：2001-04-18
申请人： Ram Voorakaranam , Abhijit Chatterjee , Pramodchandran N. Variyam , Sasikumar Cherubal , Alfred V. Gomes
发明人： Ram Voorakaranam , Abhijit Chatterjee , Pramodchandran N. Variyam , Sasikumar Cherubal , Alfred V. Gomes
IPC分类号： G06F11/263
CPC分类号： G01R31/2837
摘要： A low cost signature test for RF and analog circuits. A model is provided to predict one or more performance parameters characterizing a first electronic circuit produced by a manufacturing process subject to process variation from the output of one or more second electronic circuits produced by the same process in response to a selected test stimulus, and iteratively varying the test stimulus to minimize the error between the predicted performance parameters and corresponding measured values for the performance parameters, for determining an optimized test stimulus. A non-linear model is preferably constructed for relating signature test results employing the optimized test stimulus in manufacturing testing to circuit performance parameters.

4. 发明授权

US06625785B2 Method for diagnosing process parameter variations from measurements in analog circuits 失效
公开(公告)号：US06625785B2
公开(公告)日：2003-09-23
申请号：US09838404
申请日：2001-04-19
申请人： Abhijit Chatterjee , Sasikumar Cherubal
发明人： Abhijit Chatterjee , Sasikumar Cherubal
IPC分类号： G06F1750
CPC分类号： H01L22/20 , G06F17/5036 , G06F2217/10
摘要： A method for diagnosing process parameter variations from measurements in analog circuits. The diagnosability conditions for the accurate computation of device parameters are extended in the presence of measurement noise. In case this diagnosability condition is not met by standard test signals, a method is provided for automatically generating optimized tests that enable the computation of device parameters. The test generator explicitly optimizes the ability to compute device parameters from the test response. A cause-effect analysis engine is provided to diagnose the cause of variation in IC performance metrics in terms of the variation in device parameter values. Once the cause of parametric yield loss is diagnosed in terms of device parameters variations, the information can be used by process engineers to tune the manufacturing process to improve yield.

5. 发明授权

US06476741B2 Method and system for making optimal estimates of linearity metrics of analog-to-digital converters 失效
标题翻译：用于对模拟 - 数字转换器进行线性度量的最佳估计的方法和系统
公开(公告)号：US06476741B2
公开(公告)日：2002-11-05
申请号：US09838359
申请日：2001-04-19
申请人： Sasikumar Cherubal , Abhijit Chatterjee
发明人： Sasikumar Cherubal , Abhijit Chatterjee
IPC分类号： H03M110
CPC分类号： H03M1/109 , H03M1/12
摘要： A method and system for making optimal estimates of linearity metrics of analog-to-digital converters. A model building phase and a production test strategy are employed. During the model-building phase, a linear model an analog-to-digital converter is constructed from a set of accurately measured transition code voltages for a set of training analog-to-digital converters. During a production test of an individual analog-to-digital converter, a ramp test signal is applied to the individual analog-to-digital converter, a histogram of codes is produced, and the transition code voltages for the individual analog-to-digital converter are estimated from the resulting histogram. Linearity characteristics of the individual analog-to-digital converter may then be computed.
摘要翻译：一种用于对模数转换器的线性度量进行最佳估计的方法和系统。采用模型建立阶段和生产测试策略。在模型构建阶段期间，模拟 - 数字转换器的线性模型由一组训练模数转换器的一组准确测量的转换代码电压构成。在单个模拟 - 数字转换器的生产测试期间，斜坡测试信号被施加到单个模数转换器，产生代码直方图，并且针对各个模数转换器的转换代码电压转换器根据最终的直方图进行估计。然后可以计算各个模拟 - 数字转换器的线性特性。

6. 发明申请

US20060001562A1 Method and system for sampling a signal 有权
标题翻译：用于采样信号的方法和系统
公开(公告)号：US20060001562A1
公开(公告)日：2006-01-05
申请号：US10881576
申请日：2004-06-30
申请人： David Guidry , Sasikumar Cherubal
发明人： David Guidry , Sasikumar Cherubal
IPC分类号： H03M1/12
CPC分类号： H03M1/1245
摘要： According to one embodiment of the invention, a method of sampling a signal is provided. The method includes receiving over a signal path an analog signal generated using a first clock signal by a first device. The method also includes sampling the analog signal using a second clock signal to generate a numeric representation of at least a portion of the analog signal. The frequencies of the first and the second clock signals differ from one another by a known amount. The method also includes communicating over the signal path the numeric representation for receipt by a second device. The signal path experiences loading and at least a majority of the loading of the signal path occurs between the sampler and the second device.
摘要翻译：根据本发明的一个实施例，提供了一种采样信号的方法。该方法包括通过信号路径接收由第一设备使用第一时钟信号产生的模拟信号。该方法还包括使用第二时钟信号对模拟信号进行采样，以产生模拟信号的至少一部分的数字表示。第一和第二时钟信号的频率彼此相差已知的量。该方法还包括通过信号路径通信数字表示，以便由第二设备接收。信号路径经历负载，信号路径的至少大部分负载发生在采样器和第二设备之间。

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