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1. 发明授权

US10861575B2 Memory with a controllable I/O functional unit 有权
公开(公告)号：US10861575B2
公开(公告)日：2020-12-08
申请号：US16666164
申请日：2019-10-28
申请人： Arm Limited
发明人： Rajiv Kumar Sisodia , Renu Rawat , Paul Darren Hoxey , Vikash , Kumaraswamy Ramanathan , Sanjay Mangal , Yew Keong Chong
IPC分类号： G11C29/12 , G11C11/418 , G11C11/419 , G11C7/10 , G11C29/32 , G11C5/06
摘要： A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

2. 发明申请

US20200066365A1 Memory with a Controllable I/O Functional Unit 审中-公开
公开(公告)号：US20200066365A1
公开(公告)日：2020-02-27
申请号：US16666164
申请日：2019-10-28
申请人： Arm Limited
发明人： Rajiv Kumar Sisodia , Renu Rawat , Paul Darren Hoxey , Vikash , Kumaraswamy Ramanathan , Sanjay Mangal , Yew Keong Chong
IPC分类号： G11C29/12 , G11C11/419 , G11C11/418 , G11C29/32 , G11C7/10
摘要： A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

3. 发明授权

US10460822B2 Memory with a controllable I/O functional unit 有权
公开(公告)号：US10460822B2
公开(公告)日：2019-10-29
申请号：US15684239
申请日：2017-08-23
申请人： ARM Limited
发明人： Rajiv Kumar Sisodia , Renu Rawat , Paul Darren Hoxey , Vikash , Kumaraswamy Ramanathan , Sanjay Mangal , Yew Keong Chong
IPC分类号： G11C29/12 , G11C11/418 , G11C11/419 , G11C7/10 , G11C29/32 , G11C5/06
摘要： A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

4. 发明授权

US09324392B1 Memory device and method of performing a write operation in a memory device 有权
标题翻译：在存储器件中执行写入操作的存储器件和方法
公开(公告)号：US09324392B1
公开(公告)日：2016-04-26
申请号：US14521635
申请日：2014-10-23
申请人： ARM LIMITED
发明人： Plamen Asenov Asenov , David Anthony New , Paul Darren Hoxey
IPC分类号： G11C8/00 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/18
CPC分类号： G11C7/12 , G11C7/22 , G11C7/227 , G11C8/08 , G11C8/18 , G11C11/418 , G11C11/419
摘要： The present invention provides a technique for performing write operations within a memory device comprising an array of memory cells. Wordline driver circuitry is used to assert a wordline signal to activate an addressed memory cell in the array. Write driver circuitry is used to perform a write operation to write a data value into the addressed memory cell, and is responsive to assertion of a write assist enable signal during the write operation to implement a write assist mechanism. Further, control circuitry is used to control timing of assertion of the wordline signal in dependence on timing of assertion of the write assist enable signal. By making the timing of assertion of the wordline signal dependent on the timing at which the write assist enable signal is asserted, it has been found that writeability of the memory cells is significantly improved.
摘要翻译：本发明提供了一种用于在包括存储器单元阵列的存储器件内执行写入操作的技术。字线驱动器电路用于断言字线信号以激活阵列中寻址的存储单元。写入驱动器电路用于执行写入操作以将数据值写入寻址的存储器单元，并且响应于在写入操作期间写入辅助使能信号的确认以实现写入辅助机制。此外，控制电路用于根据写入辅助使能信号的断言的定时来控制字线信号的断言的定时。通过使得字线信号的断言定时取决于写辅助使能信号的定时，已经发现存储器单元的可写性显着提高。

5. 发明申请

US20190066814A1 Memory with a Controllable I/O Functional Unit 审中-公开
公开(公告)号：US20190066814A1
公开(公告)日：2019-02-28
申请号：US15684239
申请日：2017-08-23
申请人： ARM Limited
发明人： Rajiv Kumar Sisodia , Renu Rawat , Paul Darren Hoxey , Vikash , Kumaraswamy Ramanathan , Sanjay Mangal , Yew Keong Chong
IPC分类号： G11C29/12 , G11C11/418 , G11C11/419
CPC分类号： G11C29/1201 , G11C5/066 , G11C7/1018 , G11C7/1036 , G11C11/418 , G11C11/419 , G11C29/12015 , G11C29/32 , G11C2029/1204 , G11C2207/107
摘要： A circuit includes a bitcell array having a plurality of bitlines, and an I/O functional unit to read data stored in the bitcell array. The I/O functional unit includes a first multiplexer to select a first input port or a first bitline among a first group of bitlines, a first latch to latch the output of the first multiplexer, a second multiplexer to select a second input port or a second bitline among a second group of bitlines. The second input port is coupled to an output port of the first latch. The I/O functional unit further includes a second latch to latch the output of the second multiplexer.

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