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1. 发明授权

US09996471B2 Cache with compressed data and tag 有权
公开(公告)号：US09996471B2
公开(公告)日：2018-06-12
申请号：US15194902
申请日：2016-06-28
申请人： ARM Limited
发明人： Ali Saidi , Kshitij Sudan , Andrew Joseph Rushing , Andreas Hansson , Michael Filippo
IPC分类号： G06F12/0871 , G06F12/0873 , G06F12/0895
CPC分类号： G06F12/0871 , G06F12/0868 , G06F12/0873 , G06F12/0895 , G06F2212/305 , G06F2212/401 , G06F2212/466
摘要： Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.

2. 发明授权

US09859003B1 Selective writes in a storage element 有权
公开(公告)号：US09859003B1
公开(公告)日：2018-01-02
申请号：US15334747
申请日：2016-10-26
申请人： ARM Limited
发明人： Shidhartha Das , Andreas Hansson , Akshay Kumar , Piyush Agarwal , Azeez Jennudin Bhavnagarwala , Lucian Shifren
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C2013/0045 , G11C2013/0054 , G11C2013/0076 , G11C2013/0078 , G11C2207/2263 , G11C2213/31
摘要： A method of writing a state to a correlated electron element in a storage circuit, comprising receiving a write command to write the state into the correlated electron element; reading a stored state of the correlated electron element; comparing the state and the stored state; and enabling a write driver to write the state into the correlated electron element when the state and read state are different.

3. 发明授权

US10901884B2 Wear levelling in non-volatile memories 有权
公开(公告)号：US10901884B2
公开(公告)日：2021-01-26
申请号：US15781979
申请日：2016-12-02
申请人： Arm Limited
发明人： Andreas Lars Sandberg , Irenéus Johannes de Jong , Andreas Hansson
IPC分类号： G06F13/00 , G06F13/28 , G06F12/02 , G11C29/00 , G06F3/06 , G06F11/10 , G11C29/04
摘要： Broadly speaking, embodiments of the present technique provide an apparatus and methods for improved wear-levelling in non-volatile memory (NVM) devices. In particular, the present wear-levelling techniques operate on small blocks within a memory device, at a finer scale/granularity than that used by common wear-levelling techniques which often remap large blocks (e.g. several kilobytes) of data.

4. 发明申请

US20180365142A1 WEAR LEVELLING IN NON-VOLATILE MEMORIES 审中-公开
公开(公告)号：US20180365142A1
公开(公告)日：2018-12-20
申请号：US15781979
申请日：2016-12-02
申请人： Arm Limited
发明人： Andreas Lars SANDBERG , Irenéus Johannes de JONG , Andreas Hansson
IPC分类号： G06F12/02 , G06F11/10 , G06F3/06
摘要： Broadly speaking, embodiments of the present technique provide an apparatus and methods for improved wear-levelling in non-volatile memory (NVM) devices. In particular, the present wear-levelling techniques operate on small blocks within a memory device, at a finer scale/granularity than that used by common wear-levelling techniques which often remap large blocks (e.g. several kilobytes) of data.

5. 发明授权

US10956045B2 Apparatus and method for issuing access requests to a memory controller 有权
公开(公告)号：US10956045B2
公开(公告)日：2021-03-23
申请号：US14969414
申请日：2015-12-15
申请人： ARM Limited
发明人： Andreas Hansson , Ian Rudolf Bratt
IPC分类号： G06F3/06 , G06F13/16 , G06F12/12
摘要： An apparatus and method are provided for issuing access requests to a memory controller for a memory device whose memory structure consists of a plurality of sub-structures. The apparatus has a request interface for issuing access requests to the memory controller, each access request identifying a memory address. Within the apparatus static abstraction data is stored providing an indication of one or more of the sub-structures of the memory device, and the apparatus also stores an indication of outstanding access requests issued from the request interface. Next access request selection circuitry is then arranged to select from a plurality of candidate access requests a next access request to issue from the request interface. That selection is dependent on sub-structure indication data that is derived from application of an abstraction data function, using the static abstraction data, to the memory addresses of the candidate access requests and the outstanding access requests. Such an approach enables the apparatus to provide a series of access requests to the memory controller with the aim of enabling the memory controller to perform a more optimal access sequence with regard to the memory device.

6. 发明授权

US10339050B2 Apparatus including a memory controller for controlling direct data transfer between first and second memory modules using direct transfer commands 有权
公开(公告)号：US10339050B2
公开(公告)日：2019-07-02
申请号：US15273743
申请日：2016-09-23
申请人： ARM Limited
发明人： Andreas Hansson , Wendy Arnott Elsasser , Michael Andrew Campbell
IPC分类号： G06F12/06 , G06F13/16 , G06F12/084 , G06F12/0888 , G06F13/42
摘要： An apparatus, memory controller, memory module and method are provided for controlling data transfer in memory. The apparatus comprises a memory controller and a plurality of memory modules. The memory controller orchestrates direct data transfer by issuing a first direct transfer command to a first memory module and a second direct transfer command to a second memory module. The first memory module is responsive to receipt of the first direct transfer command to directly transmit the data for receipt by the second memory module in a way that bypasses the memory controller. The second memory module is responsive to the second direct transfer command to receive the data from the first memory module directly, rather than via the memory controller. One of the first and second memory modules may be used as a cache for data stored in the other memory module. The direct data transfer may comprise a data move or a data copy operation. This provides an efficient mechanism for transferring data between multiple memory modules coupled to the same memory controller.

7. 发明授权

US11803228B2 Multiple heterogeneous energy stores 有权
公开(公告)号：US11803228B2
公开(公告)日：2023-10-31
申请号：US15566386
申请日：2016-03-10
申请人： ARM LIMITED
发明人： Andreas Hansson , Ashley John Crawford , Stephan Diestelhorst , James Edward Myers
IPC分类号： G06F1/26 , G06F1/329 , H02J7/34 , G06F1/3228 , H02J7/00
CPC分类号： G06F1/329 , G06F1/263 , G06F1/3228 , H02J7/345 , H02J7/00714 , H02J7/007182 , H02J7/007192 , Y02D10/00
摘要： There is provided an apparatus comprising a requirement determination unit to determine an energy requirement for a system component. A status determination unit determines status information relating to a plurality of heterogeneous energy stores and actuating system control unit controls an activity of the system component in dependence on the status information relating to the plurality of heterogeneous energy stores and the energy requirement.

8. 发明授权

US11243898B2 Memory controller and method for controlling a memory device to process access requests issued by at least one master device 有权
公开(公告)号：US11243898B2
公开(公告)日：2022-02-08
申请号：US14449689
申请日：2014-08-01
申请人： ARM Limited
发明人： Andreas Hansson , Aniruddha Nagendran Udipi , Neha Agarwal
IPC分类号： G06F13/18 , G06F13/16 , G11C8/12
摘要： A memory controller and method are provided for controlling a memory device to process access requests issued by at least one master device, the memory device having a plurality of access regions. The memory controller has a pending access requests storage that buffers access requests that have been issued by a master device prior to those access requests being processed by the memory device. Access control circuitry then issues control commands to the plurality of access regions in order to control the memory device to process access requests retrieved from the pending access requests storage. A query structure is also provided that is configured to maintain, for each access region, information about the buffered access requests in the pending access requests storage, and the access control circuitry references the query structure when determining the control commands to be issued to the plurality of access regions. Such an approach enables significant performance and energy savings to be realized in control of the memory device, without requiring the contents of the pending access requests storage to be directly monitored by the access control circuitry.

9. 发明授权

US10860495B2 Storage circuitry responsive to a tag-matching command 有权
公开(公告)号：US10860495B2
公开(公告)日：2020-12-08
申请号：US16464019
申请日：2017-09-15
申请人： ARM LIMITED
发明人： Andreas Hansson , Nikos Nikoleris , Wendy Arnott Elsasser
IPC分类号： G06F12/08 , G06F12/10 , G06F12/0895 , G06F12/0864 , G11C11/16 , G11C11/406
摘要： Storage circuitry comprises an array of storage locations arranged in rows and columns, a row buffer comprising a plurality of entries each to store information from a storage location at a corresponding column of an active row of the array, and comparison circuitry responsive to a tag-matching command specifying a tag value to compare the tag value with information stored in each of a subset of two or more entries of the row buffer. The comparison circuitry identifies which of the subset of entries, if any, is a matching entry storing information matching the tag value. This allows memory technologies such as DRAM to be used more efficiently as a set-associative cache.

10. 发明授权

US11010297B2 Memory unit and method of operation of a memory unit to handle operation requests 有权
公开(公告)号：US11010297B2
公开(公告)日：2021-05-18
申请号：US16321057
申请日：2017-06-26
申请人： ARM LIMITED
发明人： Andreas Hansson
IPC分类号： G06F12/0811 , G06F12/084 , G06F12/0893 , G06F15/78 , G06F9/38
摘要： A memory unit includes a data storage to store data, an operation controller to receive operation requests issued by an upstream source, a downstream capabilities storage to store an indication of operations performable by at least one downstream memory unit, and processing circuitry to perform operations on data stored in the data storage under control of the operation controller. When an operation request to perform an operation on target data is received from the upstream request source, the operation controller is arranged to determine when to control the processing circuitry to perform the operation, and when to forward the operation to a downstream memory unit in dependence on whether the target data is stored in the data storage unit and the indication of operations performable by at least one downstream memory unit. This allows for operations to be executed at a suitable location within a memory system, taking into account not only where the data resides, but also the complexity of the operation and the capabilities of the processing circuitry provided at various memory locations within the memory system.

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