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1. 发明授权

US10216633B2 Hardware based coherency between a data processing device and interconnect 有权
公开(公告)号：US10216633B2
公开(公告)日：2019-02-26
申请号：US15141954
申请日：2016-04-29
申请人： ARM Limited
发明人： Dominic William Brown , Ashley John Crawford
IPC分类号： G06F12/08 , G06F12/0815 , G06F12/0804 , G06F12/084
摘要： There is provided a data processing device including an output port to transmit a request value to an interconnect arranged to implement a coherency protocol, to indicate a request to be subjected to the coherency protocol. An input port receives an acknowledgement value from the interconnect in response to the request value and coherency administration circuitry defines behavior rules for the data processing device in accordance with the coherency protocol and in dependence on the request value and the acknowledgement value. Storage circuitry administers data in accordance with the behavior rules. There is also provided an interconnect including an input port to receive a request value, issued by a data processing device having storage circuitry, to indicate a request for the data processing to be subjected to a coherency protocol. An output port transmits an acknowledgement value to the data processing device in response to the request value and coherency administration circuitry defines behavior rules for the interconnect in accordance with the coherency protocol and in dependence on the request value and the acknowledgement value.

2. 发明授权

US10763829B2 Counter circuitry and method 有权
公开(公告)号：US10763829B2
公开(公告)日：2020-09-01
申请号：US15683962
申请日：2017-08-23
申请人： ARM LIMITED
发明人： Ashley John Crawford , John Michael Horley
IPC分类号： H03J7/06 , H03K21/40 , G07C3/04 , G06F1/3203 , H03B5/12 , H03K9/06
摘要： Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

3. 发明授权

US10591977B2 Segregated power state control in a distributed cache system 有权
公开(公告)号：US10591977B2
公开(公告)日：2020-03-17
申请号：US14965184
申请日：2015-12-10
申请人： ARM Limited
发明人： Mark David Werkheiser , Dominic William Brown , Ashley John Crawford , Paul Gilbert Meyer
IPC分类号： G06F1/32 , G06F1/3234 , G06F12/0813 , G06F12/0831
摘要： A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.

4. 发明授权

US11409349B2 Power management 有权
公开(公告)号：US11409349B2
公开(公告)日：2022-08-09
申请号：US16420578
申请日：2019-05-23
申请人： Arm Limited
发明人： Carlos Garcia-Tobin , Jose Manuel Silva Dos Santos Marinho , Ashley John Crawford , Anouk Martha H Van Laer
IPC分类号： G06F1/32 , G06F1/3206 , G06F9/38 , G06F1/324
摘要： A data processing apparatus includes processing circuitry to process an event stream that includes one or more high power events. Tracking circuitry tracks the one or more high power events and power management circuitry manages power consumption by controlling a voltage supply and a frequency of a clock signal provided to the processing circuitry. The power management circuitry controls an extent to which execution by the processing circuitry of the high power events is restricted.

5. 发明授权

US10452110B2 Combination of control interfaces for multiple communicating domains 有权
公开(公告)号：US10452110B2
公开(公告)日：2019-10-22
申请号：US15462146
申请日：2017-03-17
申请人： ARM Limited
发明人： Dominic William Brown , Ashley John Crawford , Christopher Vincent Severino
IPC分类号： G06F1/26 , G06F13/16 , G06F1/3234 , G06F1/3287
摘要： Various implementations described herein are directed to a method and apparatus for a low power interface combiner for controlling a cross domain component in a system of two or more power domain controls. The combiner may include a first state for requesting cross domain component quiescence when a first control requests quiescence and a second state for ensuring cross domain component quiescence before accepting the first control quiescence request. The combiner may include a third state for requesting cross domain component quiescence exit when a last control requests quiescence exit and other controls have exited or are exiting quiescence. The combiner may include a fourth state for ensuring cross domain component quiescence exit before accepting the last control quiescence exit request.

6. 发明授权

US10359831B2 Cache power management 有权
公开(公告)号：US10359831B2
公开(公告)日：2019-07-23
申请号：US15447866
申请日：2017-03-02
申请人： ARM Limited
发明人： Ashley John Crawford , Andrew Christopher Rose , Tessil Thomas , David Guillen Fandos
IPC分类号： G06F1/3225 , G06F1/3234 , G06F1/3287 , G06F1/3296
摘要： A method of operating a cache and corresponding apparatus are provided. The cache is capable of being only partially powered, and a decision to reduce the proportion of the cache which is currently powered is made based on calculating a memory bandwidth equivalent of expending the current active cache leakage power on memory access. The cache hit bandwidth is compared against this memory bandwidth equivalent and when the cache hit bandwidth is less than the memory bandwidth equivalent, the proportion of the cache which is currently powered is reduced. A analogous decision may also be made and based on calculating a cache hit bandwidth equivalent for an increment increase in cache leakage power, and when the cache miss bandwidth exceeds the cache hit bandwidth equivalent, the proportion of the cache which is currently powered is increased.

7. 发明授权

US10133341B2 Delegating component power control 有权
公开(公告)号：US10133341B2
公开(公告)日：2018-11-20
申请号：US15173939
申请日：2016-06-06
申请人： ARM Limited
发明人： Dominic William Brown , Ashley John Crawford , Christopher Vincent Severino , Tessil Thomas
IPC分类号： G06F1/32 , G06F13/24
摘要： An apparatus and a corresponding method of operating the apparatus are disclosed. A component of the apparatus is capable of operating in one of at least two power modes and component power control circuitry which is communicatively coupled to the component causes the component to operate in a selected power mode of those power modes. A system power controller controls operation of the component power control circuitry by setting a power mode lock condition therein. When the power mode lock condition is met the component power control circuitry cannot change the selected power mode of the component. Power control over the component is thus partially delegated from the system power controller to the component power control circuitry.

8. 发明授权

US11803228B2 Multiple heterogeneous energy stores 有权
公开(公告)号：US11803228B2
公开(公告)日：2023-10-31
申请号：US15566386
申请日：2016-03-10
申请人： ARM LIMITED
发明人： Andreas Hansson , Ashley John Crawford , Stephan Diestelhorst , James Edward Myers
IPC分类号： G06F1/26 , G06F1/329 , H02J7/34 , G06F1/3228 , H02J7/00
CPC分类号： G06F1/329 , G06F1/263 , G06F1/3228 , H02J7/345 , H02J7/00714 , H02J7/007182 , H02J7/007192 , Y02D10/00
摘要： There is provided an apparatus comprising a requirement determination unit to determine an energy requirement for a system component. A status determination unit determines status information relating to a plurality of heterogeneous energy stores and actuating system control unit controls an activity of the system component in dependence on the status information relating to the plurality of heterogeneous energy stores and the energy requirement.

9. 发明授权

US10908667B2 Technique for managing power domains in an integrated circuit 有权
公开(公告)号：US10908667B2
公开(公告)日：2021-02-02
申请号：US16190377
申请日：2018-11-14
申请人： Arm Limited
发明人： Christopher Vincent Severino , Dominic William Brown , Ashley John Crawford
IPC分类号： G06F1/32 , G06F1/3234
摘要： An integrated circuit and method are provided for managing power domains. The integrated circuit has first circuitry provided within a first power domain, and a distributed power controller for controlling transition of the first power domain between a plurality of power states. The distributed power controller comprises at least power control circuitry in a second power domain and additional power control circuitry in a third power domain. Whilst the current power state of the first power domain is in any one of at least two of the plurality of power states, the second power domain is allowed to be placed in a power saving state where the power control circuitry loses knowledge of the current power state of the first power domain. However, the third power domain is prevented from entering that power saving state. Further, the additional power control circuitry is arranged to output a mode status signal that is then used by the power control circuitry, when the second power domain exits the power saving state, to place the power control circuitry into an initial mode of operation that is dependent on the current power state of the first power domain. This ensures that, despite the power control circuitry losing knowledge of the current power state of the first power domain whilst it is in the power saving state, no unintended consequences occur when the second power domain subsequently exits the power saving state.

10. 发明授权

US10788886B2 Controlling transitions of devices between normal state and quiescent state 有权
公开(公告)号：US10788886B2
公开(公告)日：2020-09-29
申请号：US15567707
申请日：2016-03-16
申请人： ARM LIMITED
发明人： Dominic William Brown , Christopher Vincent Severino , Ashley John Crawford
IPC分类号： G06F1/26 , G06F1/32 , G06F1/3296 , G06F1/3287 , G06F1/3203 , G06F1/3237 , G06F1/3215
摘要： A data processing apparatus has a number of devices having a normal state and a quiescent state in which the device is ready for being placed in a power saving state. Each device provides at least one preference indication indicative of a preference to operate in the normal state or the quiescent state. A controller controls a common state transition process for transitioning each of the devices 4 between the normal state and the quiescent state based on the preference indication received from each device.

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