专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080237800A1 INTEGRATED CIRCUIT HAVING RESISTOR BETWEEN BEOL INTERCONNECT AND FEOL STRUCTURE AND RELATED METHOD 有权
标题翻译： BEOL互连与FEOL结构之间的电阻集成电路及相关方法
公开(公告)号：US20080237800A1
公开(公告)日：2008-10-02
申请号：US11692336
申请日：2007-03-28
申请人： ANIL K. CHINTHAKINDI , Vincent J. McGahay
发明人： ANIL K. CHINTHAKINDI , Vincent J. McGahay
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L23/5228 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography.
摘要翻译：公开了集成电路（IC）和制造IC的方法，其中IC的结构在第一金属层下方包含后端行（BEOL）薄膜电阻器以实现较低的形貌。电阻器直接接触前端（FEOL）结构中的接触金属之一; BEOL互连中的第一金属层; 或其组合，以避免在不同形貌下形成与不同高度或接触面的接触的必要性。

2. 发明授权

US08343868B2 Device and methodology for reducing effective dielectric constant in semiconductor devices 有权
标题翻译：用于降低半导体器件中有效介电常数的器件和方法
公开(公告)号：US08343868B2
公开(公告)日：2013-01-01
申请号：US13005201
申请日：2011-01-12
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.
摘要翻译：一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻特征跨越到多个互连的侧壁。

3. 发明授权

US07345305B2 Control of liner thickness for improving thermal cycle reliability 有权
标题翻译：控制衬套厚度，提高热循环的可靠性
公开(公告)号：US07345305B2
公开(公告)日：2008-03-18
申请号：US11248719
申请日：2005-10-12
申请人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
发明人： Ronald Gene Filippi , Lynne Marie Gignac , Vincent J. McGahay , Conal Eugene Murray , Hazara Singh Rathore , Thomas M. Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58
CPC分类号： G01R31/2881
摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.
摘要翻译：公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。在结构中感兴趣的位置确定菌株。在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。可以根据结果进行预测和设计更改。

4. 发明授权

US07253105B2 Reliable BEOL integration process with direct CMP of porous SiCOH dielectric 失效
标题翻译：可靠的BEOL集成工艺与多孔SiCOH电介质的直接CMP
公开(公告)号：US07253105B2
公开(公告)日：2007-08-07
申请号：US11063152
申请日：2005-02-22
申请人： Christos D. Dimitrakopoulos , Stephen M. Gates , Vincent J. McGahay , Sanjay C. Mehta
发明人： Christos D. Dimitrakopoulos , Stephen M. Gates , Vincent J. McGahay , Sanjay C. Mehta
IPC分类号： H01L21/44
CPC分类号： H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L21/76885 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to methods of improving the fabrication of interconnect structures of the single or dual damascene type, in which there is no problem of hard mask retention or of conductivity between the metal lines after fabrication. The methods of the present invention include at least steps of chemical mechanical polishing and UV exposure or chemical repair treatment which steps improve the reliability of the interconnect structure formed. The present invention also relates to an interconnect structure which include a porous ultra low k dielectric of the SiCOH type in which the surface layer thereof has been modified so as to form a gradient layer that has both a density gradient and a C content gradient.
摘要翻译：本发明涉及改进单镶嵌型或双镶嵌型互连结构的制造方法，其中在制造之后金属线之间没有硬掩模保持或导电性问题。本发明的方法包括化学机械抛光和紫外线曝光或化学修复处理的至少步骤，这些步骤提高了形成的互连结构的可靠性。本发明还涉及一种互连结构，其包括SiCOH型的多孔超低k电介质，其中其表面层被修饰以形成具有密度梯度和C含量梯度的梯度层。

5. 发明授权

US07253100B2 Reducing damage to ulk dielectric during cross-linked polymer removal 有权
标题翻译：在交联聚合物去除期间减少对ulk电介质的损伤
公开(公告)号：US07253100B2
公开(公告)日：2007-08-07
申请号：US11164290
申请日：2005-11-17
申请人： Ronald A. DellaGuardia , Daniel C. Edelstein , Habib Hichri , Vincent J. McGahay
发明人： Ronald A. DellaGuardia , Daniel C. Edelstein , Habib Hichri , Vincent J. McGahay
IPC分类号： H10L21/4763
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31133 , H01L21/76808
摘要： Methods are disclosed for reducing damage to an ultra-low dielectric constant (ULK) dielectric during removal of a planarizing layer such as a crosslinked polymer. The methods at least partially fill an opening with an at most lightly crosslinked polymer, followed by the planarizing layer. When the at most lightly crosslinked polymer and planarizing layer are removed, the at most lightly crosslinked polymer removal is easier than removal of the planarizing layer, i.e., crosslinked polymer, and does not damage the surrounding dielectric compared to removal chemistries used for the crosslinked polymer.
摘要翻译：公开了减少在去除平坦化层例如交联聚合物期间对超低介电常数（ULK）电介质的损伤的方法。该方法至少部分地用至少轻度交联的聚合物填充开口，随后是平坦化层。当除去至多轻度交联的聚合物和平坦化层时，与用于交联聚合物的去除化学物质相比，去除至多轻度交联的聚合物去除比去除平坦化层即交联聚合物更容易，并且不损坏周围的电介质。

6. 发明授权

US07067902B2 Building metal pillars in a chip for structure support 有权
标题翻译：建筑金属支柱在一个芯片的结构支持
公开(公告)号：US07067902B2
公开(公告)日：2006-06-27
申请号：US10726140
申请日：2003-12-02
申请人： Habib Hichri , Xiao H. Liu , Vincent J. McGahay , Conal E. Murray , Jawahar P. Nayak , Thomas M. Shaw
发明人： Habib Hichri , Xiao H. Liu , Vincent J. McGahay , Conal E. Murray , Jawahar P. Nayak , Thomas M. Shaw
IPC分类号： H01L29/40
CPC分类号： H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.
摘要翻译：通过支柱堆叠，例如金属通孔柱，在IC芯片的不同和指定位置处提供，以在加工期间支撑芯片结构以及任何相关的加工应力，例如热和机械应力。这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形，并且还可以在处理或可靠性测试期间缓解任何应力，热和/或机械的积累。堆叠的通孔柱通常不电连接到任何有源线或通孔，但是在一些实施例中，堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。

7. 发明授权

US06727589B2 Dual damascene flowable oxide insulation structure and metallic barrier 有权
标题翻译：双镶嵌可流动氧化物绝缘结构和金属屏障
公开(公告)号：US06727589B2
公开(公告)日：2004-04-27
申请号：US09725862
申请日：2000-11-30
申请人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
发明人： Stephen E. Greco , John P. Hummel , Joyce Liu , Vincent J. McGahay , Rebecca Mih , Kamalesh Srivastava
IPC分类号： H01L2348
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/7684
摘要： A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.
摘要翻译：一种通过氧化FOX绝缘体的侧壁来保护半导体中的可流动的氧化物绝缘体的方法和结构，可选地将氧化的FOX侧壁氮化，然后覆盖包括侧壁在内的FOX绝缘体中的槽或多个槽的所有表面，导电二级保护层。在多层镶嵌结构中，FOX绝缘体的表面也被氧化，在其上沉积另外的氧化物层，并且沉积在氧化物层上的氮化物层。然后重复步骤以获得可比较的镶嵌结构。材料可以变化，并且每个镶嵌层可以是单镶嵌层或双镶嵌层。

8. 发明授权

US06387754B2 Method of forming an on-chip decoupling capacitor with bottom hardmask 失效
标题翻译：用底部硬掩模形成片上去耦电容器的方法
公开(公告)号：US06387754B2
公开(公告)日：2002-05-14
申请号：US09887381
申请日：2001-06-22
申请人： Timothy J. Dalton , Andrew P. Cowley , Peter A. Emmi , Erdem Kaltalioglu , Vincent J. McGahay
发明人： Timothy J. Dalton , Andrew P. Cowley , Peter A. Emmi , Erdem Kaltalioglu , Vincent J. McGahay
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/32136 , H01L21/32139
摘要： An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.
摘要翻译：片上垂直堆叠的去耦电容器包括形成在电容器电介质和下电极之间的硬掩模膜。用于形成电容器的制造工艺利用了硬掩膜，并且使电容器能够在低k电介质材料上形成。由于硬掩模的存在，在用于形成电容器的蚀刻和剥离工艺期间，底层的低k介电材料的攻击被抑制。低k电介质膜提供了在低k电介质材料中形成的相邻导线之间降低的寄生电容，因此提供了更高的集成度。

9. 发明授权

US06348736B1 In situ formation of protective layer on silsesquioxane dielectric for dual damascene process 有权
标题翻译：在双镶嵌工艺中在倍半硅氧烷电介质上原位形成保护层
公开(公告)号：US06348736B1
公开(公告)日：2002-02-19
申请号：US09429257
申请日：1999-10-29
申请人： Vincent J. McGahay , John P. Hummel , Joyce Liu , Rebecca Mih , Kamalesh Srivastava , Robert Cook , Stephen E. Greco
发明人： Vincent J. McGahay , John P. Hummel , Joyce Liu , Rebecca Mih , Kamalesh Srivastava , Robert Cook , Stephen E. Greco
IPC分类号： H01L2348
CPC分类号： H01L21/76831 , H01L21/02134 , H01L21/02137 , H01L21/0234 , H01L21/02362 , H01L21/31144 , H01L21/3122 , H01L21/3124 , H01L21/76807
摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.
摘要翻译：抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。在电介质材料上原位形成第一保护层，例如通过将材料暴露于含氧或含氟的等离子体中。此外，通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或从电介质材料释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多个可能损坏可流动的氧化物材料的其他材料。第一保护层和表面保护层可以通过基本相同的方法形成。因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

10. 发明授权

US08129286B2 Reducing effective dielectric constant in semiconductor devices 有权
标题翻译：降低半导体器件中的有效介电常数
公开(公告)号：US08129286B2
公开(公告)日：2012-03-06
申请号：US12139803
申请日：2008-06-16
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.
摘要翻译：制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成亚光刻特征跨越至少一个互连的侧壁。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式