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1. 发明授权

US09824923B2 Semiconductor device and method of forming conductive pillar having an expanded base 有权
公开(公告)号：US09824923B2
公开(公告)日：2017-11-21
申请号：US13468981
申请日：2012-05-10
申请人： Dzafir Shariff , Kwong Loon Yam , Lai Yee Chia , Yung Kuan Hsiao
发明人： Dzafir Shariff , Kwong Loon Yam , Lai Yee Chia , Yung Kuan Hsiao
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/768 , H01L25/065 , H01L23/00 , H01L21/683
CPC分类号： H01L21/76898 , H01L21/6836 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2221/68327 , H01L2221/6834 , H01L2224/0332 , H01L2224/0345 , H01L2224/0346 , H01L2224/03472 , H01L2224/0401 , H01L2224/05023 , H01L2224/05025 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05554 , H01L2224/05555 , H01L2224/05568 , H01L2224/05571 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/06181 , H01L2224/1132 , H01L2224/1145 , H01L2224/1146 , H01L2224/11472 , H01L2224/11849 , H01L2224/13017 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/83192 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00011 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/11 , H01L2224/03 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/01074 , H01L2924/01082 , H01L2924/01029 , H01L2924/01007 , H01L2224/81 , H01L2224/83 , H01L2924/01023 , H01L2924/04941 , H01L2224/81805
摘要： A semiconductor device has a first semiconductor die and conductive vias in the first semiconductor die. The conductive vias can be formed by extending the vias partially through a first surface of the first semiconductor die. A portion of a second surface of the first semiconductor die is removed to expose the conductive vias. A plurality of conductive pillars is formed over the first surface the first semiconductor die. The conductive pillars include an expanded base electrically connected to the conductive vias. A width of the expanded base of the conductive pillars is greater than a width of a body of the conductive pillars. A conductive layer is formed over a second surface of the first semiconductor die. The conductive layer is electrically connected to the conductive vias. A second semiconductor die is mounted to the first semiconductor die with a second conductive pillar having an expanded base.

2. 发明申请

US20130127018A1 Semiconductor Device and Method of Forming Reconstituted Wafer with Larger Carrier to Achieve More EWLB Packages per Wafer with Encapsulant Deposited Under Temperature and Pressure 有权
公开(公告)号：US20130127018A1
公开(公告)日：2013-05-23
申请号：US13366008
申请日：2012-02-03
申请人： Yoke Hor Phua , Yung Kuan Hsiao
发明人： Yoke Hor Phua , Yung Kuan Hsiao
IPC分类号： H01L23/544 , H01L21/56
CPC分类号： H01L22/30 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L22/10 , H01L23/3128 , H01L24/19 , H01L24/20 , H01L24/96 , H01L2221/68318 , H01L2221/68327 , H01L2221/68381 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/73265 , H01L2924/01029 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要： A semiconductor wafer has a plurality of semiconductor die distributed over a surface area. The semiconductor die are singulated from the semiconductor wafer. The semiconductor die are mounted to a carrier to form a reconstituted semiconductor wafer. The carrier has a surface area 10-50% larger than the surface area of the semiconductor wafer. The number of semiconductor die mounted to the carrier is greater than a number of semiconductor die singulated from the semiconductor wafer. The reconstituted wafer is mounted within a chase mold. The chase mold is closed with the semiconductor die disposed within a cavity of the chase mold. An encapsulant is dispersed around the semiconductor die within the cavity under temperature and pressure. The encapsulant can be injected into the cavity of the chase mold. The reconstituted wafer is removed from the chase mold. An interconnect structure is formed over the reconstituted wafer.

3. 发明授权

US07446398B2 Bump pattern design for flip chip semiconductor package 有权
标题翻译：凸块图案设计用于倒装芯片半导体封装
公开(公告)号：US07446398B2
公开(公告)日：2008-11-04
申请号：US11461663
申请日：2006-08-01
申请人： Pao-Kang Niu , Pei-Haw Tsao , Hao-Yi Tsai , Yung-Kuan Hsiao , Chung Yu Wang , Shang-Yun Hou , Lin Yu-Ting
发明人： Pao-Kang Niu , Pei-Haw Tsao , Hao-Yi Tsai , Yung-Kuan Hsiao , Chung Yu Wang , Shang-Yun Hou , Lin Yu-Ting
IPC分类号： H01L23/48 , H01L23/488 , H01L23/498
CPC分类号： H01L24/12 , H01L23/49816 , H01L23/49838 , H01L24/81 , H01L2224/0554 , H01L2224/05552 , H01L2224/05573 , H01L2224/13099 , H01L2224/8119 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01068 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/30107 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central portion and a peripheral portion with a transition portion therebetween. The transition portion has a lower pattern density than the central portion and peripheral portions. In the peripheral portion is at least one outer portion having a pattern density less than the average pattern density of the central portion. The outer portions of reduced pattern density may be the corner sections in a rectangular bump pattern and may further include channels that are void of contact pads. The peripheral portion may include an average pitch between most of the rows and columns, but also an increased pitch between some adjacent rows and columns.
摘要翻译：用于倒装芯片半导体封装的凹凸图案设计包括形成在封装衬底上的接触焊盘的图案。每个接触垫适于从附接到其上的半导体芯片接收相应的焊料凸块。该图案包括中间部分和周边部分，其间具有过渡部分。过渡部分具有比中心部分和周边部分更低的图案密度。在周边部分中至少有一个图案密度小于中心部分的平均图案密度的外部部分。减小图案密度的外部部分可以是矩形凸起图案中的角部，并且还可以包括无接触垫的通道。周边部分可以包括大多数行和列之间的平均间距，但是也可以在一些相邻行和列之间增加间距。

4. 发明申请

US20080029876A1 BUMP PATTERN DESIGN FOR FLIP CHIP SEMICONDUCTOR PACKAGE 有权
标题翻译：用于片状半导体封装的BUMP图案设计
公开(公告)号：US20080029876A1
公开(公告)日：2008-02-07
申请号：US11461663
申请日：2006-08-01
申请人： Pao-Kang Niu , Pei-Haw Tsao , Hao-Yi Tsai , Yung-Kuan Hsiao , Chung Yu Wang , Shang-Yun Hou , Lin Yu-Ting
发明人： Pao-Kang Niu , Pei-Haw Tsao , Hao-Yi Tsai , Yung-Kuan Hsiao , Chung Yu Wang , Shang-Yun Hou , Lin Yu-Ting
IPC分类号： H01L23/48
CPC分类号： H01L24/12 , H01L23/49816 , H01L23/49838 , H01L24/81 , H01L2224/0554 , H01L2224/05552 , H01L2224/05573 , H01L2224/13099 , H01L2224/8119 , H01L2224/8121 , H01L2224/81815 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01068 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/30107 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A bump pattern design for flip chip semiconductor packages includes a pattern of contact pads formed on a package substrate. Each contact pad is adapted to receive a corresponding solder bump from a semiconductor chip attached thereto. The pattern includes a central portion and a peripheral portion with a transition portion therebetween. The transition portion has a lower pattern density than the central portion and peripheral portions. In the peripheral portion is at least one outer portion having a pattern density less than the average pattern density of the central portion. The outer portions of reduced pattern density may be the corner sections in a rectangular bump pattern and may further include channels that are void of contact pads. The peripheral portion may include an average pitch between most of the rows and columns, but also an increased pitch between some adjacent rows and columns.
摘要翻译：用于倒装芯片半导体封装的凹凸图案设计包括形成在封装衬底上的接触焊盘的图案。每个接触垫适于从附接到其上的半导体芯片接收相应的焊料凸块。该图案包括中间部分和周边部分，其间具有过渡部分。过渡部分具有比中心部分和周边部分更低的图案密度。在周边部分中至少有一个图案密度小于中心部分的平均图案密度的外部部分。减小图案密度的外部部分可以是矩形凸起图案中的角部，并且还可以包括无接触垫的通道。周边部分可以包括大多数行和列之间的平均间距，但是也可以在一些相邻行和列之间增加间距。

5. 发明授权

US6107155A Method for making a more reliable storage capacitor for dynamic random access memory (DRAM) 有权
标题翻译：为动态随机存取存储器（DRAM）制造更可靠的存储电容器的方法
公开(公告)号：US6107155A
公开(公告)日：2000-08-22
申请号：US131118
申请日：1998-08-07
申请人： Yung-Kuan Hsiao , Cheng-Ming Wu , Yu-Hua Lee
发明人： Yung-Kuan Hsiao , Cheng-Ming Wu , Yu-Hua Lee
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10873
摘要： A modified method for forming stacked capacitors for DRAMs which circumvents oxide erosion due to misalignment is described. A planar silicon oxide (SiO.sub.2) first insulating layer is formed over device areas. First openings are etched for capacitor node contacts. A polysilicon layer is deposited and etched back to form node contacts in the first openings, which are generally recessed due to overetching to completely remove the polysilicon on the insulating surface. A Si.sub.3 N.sub.4 etch-stop layer is deposited to protect the exposed sidewalls in the first openings. A disposable second SiO.sub.2 insulating layer is deposited and second openings are etched over and to the node contacts for forming bottom electrodes. A conformal second polysilicon layer is deposited and chemically/mechanically polished back to form the bottom electrodes in the second openings. The second insulating layer is removed by wet etching to the etch-stop layer. When the second openings are misaligned over the node contact openings, the Si.sub.3 N.sub.4 on the sidewalls protects the SiO.sub.2 first insulating layer from being eroded over the devices on the substrate. The capacitors are now completed by forming an inter-electrode dielectric layer on the bottom electrodes, and depositing and patterning a third polysilicon layer for top electrodes.
摘要翻译：描述了一种用于形成用于DRAM的堆叠电容器的修改方法，其规避了由于未对准引起的氧化物侵蚀。在器件区域上形成平面氧化硅（SiO 2）第一绝缘层。第一个开口蚀刻电容器节点触点。沉积多晶硅层并将其回蚀刻以形成第一开口中的节点接触，其通常由于过蚀刻而凹陷以完全去除绝缘表面上的多晶硅。沉积Si 3 N 4蚀刻停止层以保护第一开口中暴露的侧壁。沉积一次性第二SiO 2绝缘层，并且在节点触点上蚀刻第二开口并形成底部电极。沉积保形第二多晶硅层并在第二开口中化学/机械抛光以形成底部电极。通过湿法蚀刻去除蚀刻停止层来除去第二绝缘层。当第二开口在节点接触开口上不对准时，侧壁上的Si 3 N 4保护SiO 2第一绝缘层免受衬底上的器件的侵蚀。现在通过在底部电极上形成电极间电介质层，并沉积和构图顶部电极的第三多晶硅层来完成电容器。

6. 发明授权

US6030879A Method of reducing particles during the manufacturing of fin or cylinder capacitors on a wafer 失效
标题翻译：在制造晶圆上的翅片或圆筒电容器时减小颗粒的方法
公开(公告)号：US6030879A
公开(公告)日：2000-02-29
申请号：US835314
申请日：1997-04-07
申请人： Yuan-Chang Huang , Yung-Kuan Hsiao , Dah Jong Ou Yang
发明人： Yuan-Chang Huang , Yung-Kuan Hsiao , Dah Jong Ou Yang
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/20
CPC分类号： H01L27/10852 , H01L28/87 , H01L28/91
摘要： The present invention is a method for reducing particles during the manufacturing of fin or cylinder capacitors on a wafer. This invention utilizes a negative photoresist wafer edge exposure process to protect the edge of a wafer. This prevents polysilicon peeling from the edge of the wafer so as to reduce the defects and particles appearing on the wafer.
摘要翻译：本发明是在晶片上制造翅片或圆筒电容器时减少颗粒的方法。本发明利用负光致抗蚀剂晶片边缘曝光工艺来保护晶片的边缘。这样可以防止多晶硅从晶片的边缘剥离，从而减少出现在晶片上的缺陷和颗粒。

7. 发明授权

US6004857A Method to increase DRAM capacitor via rough surface storage node plate 有权
标题翻译：通过粗糙表面存储节点板增加DRAM电容的方法
公开(公告)号：US6004857A
公开(公告)日：1999-12-21
申请号：US154846
申请日：1998-09-17
申请人： Yung-Kuan Hsiao , Chen-Jong Wang
发明人： Yung-Kuan Hsiao , Chen-Jong Wang
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/70
CPC分类号： H01L28/84 , H01L28/91 , H01L27/10852
摘要： A process for forming a crown shaped, storage node structure, for a DRAM capacitor structure, with a roughened top surface topology, needed for increased surface area, has been developed. The process features the use of a tungsten silicide layer, used as a component of the storage node structure, with the tungsten silicide layer, subjected to subsequent procedures, providing the roughened top surface topology for the storage node structure. The tungsten silicide layer, after deposition, is subjected to an oxidation procedure, followed by removal of the formed oxide layer, from a bottom portion of unoxidized tungsten silicide layer, resulting in the desired, roughened top surface topology, of the bottom portion of unoxidized tungsten silicide.
摘要翻译：已经开发了用于形成具有粗糙顶表面拓扑的DRAM电容器结构的冠形存储节点结构的用于增加表面积所需的方法。该方法的特征在于，将硅化钨层用作存储节点结构的一部分，与硅化钨层一起进行后续工序，为存储节点结构提供粗糙化的顶表面拓扑。沉积后的硅化钨层经过氧化处理，然后从未氧化的硅化钨层的底部除去形成的氧化物层，得到未氧化的底部部分所需的粗糙的顶表面拓扑结构硅化钨

8. 发明授权

US08766426B2 Integrated circuit packaging system with warpage control and method of manufacture thereof 有权
标题翻译：具有翘曲控制的集成电路封装系统及其制造方法
公开(公告)号：US08766426B2
公开(公告)日：2014-07-01
申请号：US12890161
申请日：2010-09-24
申请人： Hin Hwa Goh , Xusheng Bao , Yung Kuan Hsiao , Kang Chen , Rui Huang
发明人： Hin Hwa Goh , Xusheng Bao , Yung Kuan Hsiao , Kang Chen , Rui Huang
IPC分类号： H01L23/02
CPC分类号： H01L23/544 , H01L23/055 , H01L23/10 , H01L23/552 , H01L23/562 , H01L24/16 , H01L2224/81005 , H01L2224/81007 , H01L2924/14 , H01L2924/16152 , H01L2924/16235 , H01L2924/167 , H01L2924/1676 , H01L2924/3511 , H01L2924/00
摘要： A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit device having component connectors directly on the carrier; placing a restraint structure over the integrated circuit device for controlling warpage of the integrated circuit device during bonding of the component connectors to the carrier causing some of the component connectors to separate from the carrier; and bonding all of the component connectors to the carrier.
摘要翻译：一种集成电路封装系统的制造方法，包括：提供载体; 将具有部件连接器的集成电路装置安装在载体上; 在所述集成电路装置上放置约束结构，用于控制所述部件连接器与所述载体接合期间所述集成电路装置的翘曲，从而使所述部件连接器中的一些与所述载体分离; 并将所有组件连接器连接到载体上。

9. 发明授权

US08455991B2 Integrated circuit packaging system with warpage control and method of manufacture thereof 有权
标题翻译：具有翘曲控制的集成电路封装系统及其制造方法
公开(公告)号：US08455991B2
公开(公告)日：2013-06-04
申请号：US12890338
申请日：2010-09-24
申请人： Yung Kuan Hsiao , Xusheng Bao , Kang Chen , Hin Hwa Goh , Rui Huang
发明人： Yung Kuan Hsiao , Xusheng Bao , Kang Chen , Hin Hwa Goh , Rui Huang
IPC分类号： H01L21/56
CPC分类号： H01L23/4334 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/93 , H01L24/94 , H01L24/97 , H01L25/0655 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68368 , H01L2221/68381 , H01L2224/16225 , H01L2224/27436 , H01L2224/32225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/8101 , H01L2224/81095 , H01L2224/81815 , H01L2224/8385 , H01L2224/92 , H01L2224/92125 , H01L2224/92242 , H01L2224/93 , H01L2224/94 , H01L2224/97 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/301 , H01L2924/351 , H01L2924/3511 , H01L2224/81 , H01L2224/83 , H01L2224/11 , H01L21/78 , H01L2924/00012 , H01L2924/00 , H01L2924/3512 , H01L2924/00014
摘要： A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.
摘要翻译：一种集成电路封装系统的制造方法，包括：提供具有芯片互连的集成电路器件; 将附着层直接施加在集成电路装置上; 将装置加强件附接到具有附接层的集成电路装置; 将芯片载体附接到与集成电路器件连接的器件加强件的芯片互连件，用于控制集成电路器件的翘曲，以防止翘曲导致芯片互连在将芯片互连连接到芯片互连期间与芯片载体分离芯片载体; 以及在芯片载体和集成电路器件之间施加底部填充物，以控制所有芯片互连件与芯片载体的连接性。

10. 发明授权

US08421212B2 Integrated circuit packaging system with active surface heat removal and method of manufacture thereof 有权
标题翻译：具有活性表面除热的集成电路封装系统及其制造方法
公开(公告)号：US08421212B2
公开(公告)日：2013-04-16
申请号：US12887681
申请日：2010-09-22
申请人： Kang Chen , Xusheng Bao , Rui Huang , Yung Kuan Hsiao , Hin Hwa Goh
发明人： Kang Chen , Xusheng Bao , Rui Huang , Yung Kuan Hsiao , Hin Hwa Goh
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L21/568 , H01L23/13 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L24/14 , H01L24/16 , H01L24/73 , H01L24/92 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/1403 , H01L2224/14051 , H01L2224/16245 , H01L2224/24155 , H01L2224/32245 , H01L2224/73209 , H01L2224/92133 , H01L2224/92135 , H01L2224/97 , H01L2924/01029 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.
摘要翻译：一种集成电路封装系统的制造方法，包括：提供具有结构底侧，结构顶侧和空腔的互连结构，所述结构底侧电连接到所述结构顶侧; 将集成电路完全安装在腔内，该集成电路具有与结构顶侧共面的有源侧; 形成部分覆盖所述互连结构和所述集成电路的封装，所述封装具有与所述结构顶侧和所述有源侧共面的封装顶侧; 在结构顶侧上形成顶部再钝化层和封装; 并将散热器安装在顶部再钝化层上，以从活动侧去除热量。

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