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1. 发明申请

US20120072810A1 ERROR CORRECTION CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE CIRCUIT 审中-公开
标题翻译：错误校正电路和方法以及包括电路的半导体存储器件
公开(公告)号：US20120072810A1
公开(公告)日：2012-03-22
申请号：US13239534
申请日：2011-09-22
申请人： Yong-Tae YIM , Yun-Ho CHOI
发明人： Yong-Tae YIM , Yun-Ho CHOI
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： G11C7/1006 , G06F11/1008 , G11C2029/0411 , G11C2207/104
摘要： An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.
摘要翻译：提供了纠错电路，误差校正方法以及包括误差校正电路的半导体存储器件。误差校正电路包括部分校正子发生器，第一和第二误差位置检测器，系数计算器和确定器。部分综合征发生器使用编码数据计算至少两个部分综合征。第一误差位置检测器使用部分综合征的一部分来计算第一误差位置。系数计算器使用至少两个部分综合征计算误差位置方程的系数。确定器基于系数确定错误类型。第二错误位置检测器可选地基于错误类型计算第二错误位置。

2. 发明申请

US20100125916A1 APPARATUS AND METHOD FOR CONTROLLING CONTENT 审中-公开
标题翻译：用于控制内容的装置和方法
公开(公告)号：US20100125916A1
公开(公告)日：2010-05-20
申请号：US12564217
申请日：2009-09-22
申请人： Yun-ho CHOI , Yong-Kuk YOU
发明人： Yun-ho CHOI , Yong-Kuk YOU
IPC分类号： G06F21/00
CPC分类号： H04L63/10 , G06F21/10 , G06F21/80 , G06F2221/2129
摘要： An apparatus and method for controlling content are provided. A memory which stores storage medium information regarding a storage medium, and a main control unit which groups a plurality of contents in the storage medium into a plurality of groups, allocates a group nonce to each group, stores the group nonce in the storage medium, and if a move of at least one content item of the plurality of content items is requested, controls the move of the content item based on whether the storage medium information contains an identifier or a group nonce of a first target group including the requested content item.
摘要翻译：提供了一种用于控制内容的装置和方法。存储关于存储介质的存储介质信息的存储器和将存储介质中的多个内容分组成多个组的主控制单元，将组随机数分配给每个组，将组随机数存储在存储介质中，并且如果请求了所述多个内容项目中的至少一个内容项目的移动，则基于所述存储介质信息是否包含包括所请求的内容项目的第一目标组的标识符或组随机数来控制所述内容项目的移动。

3. 发明申请

US20090097656A1 ELECTRONIC DEVICE AND ENCRYPTION METHOD THEREOF 有权
标题翻译：电子设备及其加密方法
公开(公告)号：US20090097656A1
公开(公告)日：2009-04-16
申请号：US12046790
申请日：2008-03-12
申请人： Yun-ho CHOI
发明人： Yun-ho CHOI
IPC分类号： H04L9/06
CPC分类号： H04L9/0822 , H04L9/0891 , H04L2209/601
摘要： An electronic device and an encryption method thereof are provided. The electronic device includes a control unit which encrypts an encryption key using an inherent key, and transmits the encrypted encryption key and a key index corresponding to the inherent key to a recording medium. Accordingly, encrypted content stored in a recording medium can be decrypted when an electronic device is malfunctioning or replaced with a new one.
摘要翻译：提供电子设备及其加密方法。电子设备包括使用固有密钥加密加密密钥的控制单元，并将加密的加密密钥和与该固有密钥对应的密钥索引发送到记录介质。因此，当电子设备发生故障或用新的更换时，可以解密存储在记录介质中的加密内容。

4. 发明申请

US20090039960A1 LOW POWER CONSUMING MIXED MODE POWER AMPLIFIER 失效
标题翻译：低功耗混合模式功率放大器
公开(公告)号：US20090039960A1
公开(公告)日：2009-02-12
申请号：US12023449
申请日：2008-01-31
申请人： Min PARK , Tae-Young Kang , Byoung-Gun Choi , Yun-Ho Choi , Byung-Jo Kim , Young-Ho Kim , Kyung-Hwan Park , Seok-Bong Hyun , Nak-Woong Eum
发明人： Min PARK , Tae-Young Kang , Byoung-Gun Choi , Yun-Ho Choi , Byung-Jo Kim , Young-Ho Kim , Kyung-Hwan Park , Seok-Bong Hyun , Nak-Woong Eum
IPC分类号： H03G3/30 , H03F3/68
CPC分类号： H03G3/3042 , H03F1/0261 , H03F1/0277 , H03F1/32 , H03F3/211 , H03F3/72 , H03F2200/318 , H03F2200/451 , H03F2203/21103 , H03F2203/21139 , H03F2203/7233
摘要： Provided is a low power consuming mixed mode amplifier. The power amplifier includes: a low output amplifier circuit generating a power amplified result having high efficiency in a low output mode the most frequently used; a high output amplifier circuit generating an amplified result having
摘要翻译：提供了一种低功耗混合模式放大器。功率放大器包括：低输出放大器电路，在最常用的低输出模式中产生具有高效率的功率放大结果; 产生具有放大结果的高输出放大器电路

5. 发明申请

US20080215872A1 METHOD OF BOOTING ELECTRONIC DEVICE AND METHOD OF AUTHENTICATING BOOT OF ELECTRONIC DEVICE 有权
标题翻译：电子设备的制作方法及电子设备引导方法
公开(公告)号：US20080215872A1
公开(公告)日：2008-09-04
申请号：US11964270
申请日：2007-12-26
申请人： Yun-ho CHOI , Choon-sik JUNG
发明人： Yun-ho CHOI , Choon-sik JUNG
IPC分类号： G06F9/00
CPC分类号： G06F21/575
摘要： Provided is a method of booting an electronic device including a host central processing unit (CPU) and a security module. The method includes: the host CPU starting to boot a system by using boot information in response to a reset or power on event of the electronic device; and when an authentication start instruction is not received by the security module from the host CPU until a first predetermined period elapses after an occurrence of the reset or power on event of the electronic device, controlling an operation of the host CPU by the security module. According to the method, when the authentication start instruction is received before the first predetermined period elapses, the security module authenticates the boot information and controls the operation of the host CPU based on an authentication result. A method of authenticating a boot of the electronic device in the security module is also provided.
摘要翻译：提供一种引导包括主机中央处理单元（CPU）和安全模块的电子设备的方法。该方法包括：主机CPU通过使用引导信息来启动系统，以响应电子设备的复位或开机事件; 并且当在电子设备的复位或开机事件发生之后经过第一预定时间段之前，当安全模块从主机CPU接收到认证开始指令时，由安全模块控制主机CPU的操作。根据该方法，当在第一预定时间段之前接收到认证开始指令时，安全模块基于认证结果认证引导信息并控制主机CPU的操作。还提供了一种在安全模块中验证电子设备的引导的方法。

6. 发明授权

US07391864B2 Apparatus and method for hierarchical encryption 失效
标题翻译：用于分层加密的装置和方法
公开(公告)号：US07391864B2
公开(公告)日：2008-06-24
申请号：US10623800
申请日：2003-07-22
申请人： Yang-lim Choi , Yun-ho Choi , Yun-sang Kim
发明人： Yang-lim Choi , Yun-ho Choi , Yun-sang Kim
IPC分类号： H04L9/12
CPC分类号： H04N7/1675 , H04N21/23476 , H04N21/63345 , H04N21/63775
摘要： An apparatus and method to encrypt data having hierarchical information are provided. The apparatus includes an N-th layer key generator, which generates an N-th layer key, an (N+1)-th layer key generator, which generates an (N+1)-th layer key by applying the N-th layer key to a predetermined function, an N-th layer data encryptor, which encrypts N-th layer data using the N-th layer key, and an (N+1)-th layer data encryptor, which encrypts (N+1)-th layer data using the (N+1)-th layer key.
摘要翻译：提供了一种加密具有分层信息的数据的装置和方法。该装置包括生成第N层密钥的第N层密钥生成器，第（N + 1）层密钥生成器，其通过应用第N层密钥生成第（N + 1）层密钥第N层数据加密器，其使用第N层密钥对第N层数据进行加密;第（N + 1）层数据加密器，其加密（N + 1）层密钥，使用第（N + 1）层密钥的第二层数据。

7. 发明申请

US20060072763A1 Apparatus and method for storing data 审中-公开
标题翻译：用于存储数据的装置和方法
公开(公告)号：US20060072763A1
公开(公告)日：2006-04-06
申请号：US11244007
申请日：2005-10-06
申请人： Yong-kuk You , Yun-ho Choi , Chi-hurn Kim
发明人： Yong-kuk You , Yun-ho Choi , Chi-hurn Kim
IPC分类号： H04L9/00
CPC分类号： H04L9/0894 , H04L2209/60
摘要： Provided are an apparatus and method for storing data. The apparatus includes a directory key generator generating a directory key required for encrypting and decrypting the data by inputting a device-specific key to a key generating function, the device-specific key being unique information allocated to the device and stored in a secure region of the device. The data is stored in at least one directory, and the directory key is used in encrypting and decrypting the data in units of directories. Accordingly, it is possible to minimize consumption of resources required to encrypt and decrypt the data.
摘要翻译：提供了一种用于存储数据的装置和方法。该设备包括目录密钥生成器，其通过向密钥生成功能输入特定于设备的密钥来生成用于加密和解密数据所需的目录密钥，该设备专用密钥是分配给该设备的唯一信息并存储在该安全区域中装置。数据存储在至少一个目录中，目录密钥用于以目录为单位加密和解密数据。因此，可以最小化对数据进行加密和解密所需的资源的消耗。

8. 发明授权

US06343036B1 Multi-bank dynamic random access memory devices having all bank precharge capability 有权
标题翻译：具有全部预充电能力的多组动态随机存取存储器件
公开(公告)号：US06343036B1
公开(公告)日：2002-01-29
申请号：US09157271
申请日：1998-09-18
申请人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
发明人： Churoo Park , Hyun-Soon Jang , Chull-Soo Kim , Myung-Ho Kim , Seung-Hun Lee , Si-Yeol Lee , Ho-Cheol Lee , Tae-Jin Kim , Yun-Ho Choi
IPC分类号： G11C700
CPC分类号： G11C7/1018 , G11C7/1045 , G11C7/1072 , G11C7/222 , G11C7/225 , G11C11/406 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/4082 , G11C11/4087 , G11C2207/2281
摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.
摘要翻译：能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于灭活信号在预充电循环中工作。

9. 发明授权

US5964873A Method for updating a ROM BIOS 失效
标题翻译：更新ROM BIOS的方法
公开(公告)号：US5964873A
公开(公告)日：1999-10-12
申请号：US12487
申请日：1998-01-23
申请人： Yun-Ho Choi
发明人： Yun-Ho Choi
IPC分类号： G06F9/06 , G06F9/24 , G06F9/445
CPC分类号： G06F8/65
摘要： A method for updating a ROM BIOS includes the following steps: a step for reading an image data of a ROM BIOS which is to be updated; a step for reading a ROM BIOS image data from a ROM BIOS; a step for reading a new ROM BIOS image data from an auxiliary memory; a step for reading a new user information; a step for converting the new user information into an image data; a step for updating the new ROM BIOS image data and user information in the ROM BIOS. Since the user updates a ROM BIOS image data for oneself, the user information displayed during a POST operation can be displayed in the user's characteristic message. Therefore, the user can recognize one's computer through unique characteristics that are displayed on a monitor and easily identify one's computer among many different computers.
摘要翻译：一种用于更新ROM BIOS的方法包括以下步骤：读取要更新的ROM BIOS的图像数据的步骤; 从ROM BIOS读取ROM BIOS图像数据的步骤; 从辅助存储器读取新的ROM BIOS图像数据的步骤; 阅读新用户信息的步骤; 将新用户信息转换为图像数据的步骤; 在ROM BIOS中更新新的ROM BIOS图像数据和用户信息的步骤。由于用户更新自己的ROM BIOS图像数据，所以在POST操作期间显示的用户信息可以显示在用户的特征消息中。因此，用户可以通过显示在显示器上的独特特征来识别自己的计算机，并且可以在许多不同的计算机之间轻松识别自己的计算机。

10. 发明授权

US5610869A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5610869A
公开(公告)日：1997-03-11
申请号：US511815
申请日：1995-08-07
申请人： Seung-Moon Yoo , Ejaz ul Haq , Yun-Ho Choi , Soo-In Cho , Dae-Je Chin , Nam-Soo Kang , Seung-Hun Lee
发明人： Seung-Moon Yoo , Ejaz ul Haq , Yun-Ho Choi , Soo-In Cho , Dae-Je Chin , Nam-Soo Kang , Seung-Hun Lee
IPC分类号： G11C5/14 , H02M3/07 , G11C13/00
CPC分类号： H02M3/07 , G11C5/145
摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.
摘要翻译：半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作根据检测信号可变。因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

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