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    • 1. 发明授权
    • Frame structure for vehicle
    • 车架结构
    • US08641131B2
    • 2014-02-04
    • US13281088
    • 2011-10-25
    • Masanori HondaChikara KawamuraShin SasakiChikara TanakaYushi MatsudaYukinori Nakajima
    • Masanori HondaChikara KawamuraShin SasakiChikara TanakaYushi MatsudaYukinori Nakajima
    • B60R19/18
    • B62D25/04B62D25/025B62D29/005
    • In a frame structure for a vehicle having a reinforcement body provided inside a frame body, the frame body comprises a first face portion and a second face portion extending in a direction substantially perpendicular to a rotational-axis direction of a bending moment occurring when a torsional load acts on a vehicle body, and third face portions positioned between the first and second face portions, and the reinforcement body comprises third-face connection portions connected to the third face portions, a first-face connection portion connected to the first face portion at a corner portion, a first-face non-contact portion provided away from the first face portion, a second-face connection portion connected to the second face portion at a corner portion, and a second-face non-contact portion provided away from the second face portion.
    • 在具有设置在框体内的加强体的车辆的框架结构中,框架体包括第一面部和第二面部,该第一面部和第二面部在与扭转时产生的弯矩的旋转轴线方向大致正交的方向延伸 负载作用在车身上,第三面部分位于第一和第二面部之间,加强体包括连接到第三面部的第三面连接部,与第一面部连接的第一面连接部, 拐角部分,远离第一面部分设置的第一面非接触部分,在拐角处连接到第二面部分的第二面连接部分和远离第二面部分设置的第二面非接触部分 第二面部。
    • 3. 发明申请
    • Detection rate calculation method of test pattern, recording medium, and detection rate calculation apparatus of test pattern
    • 测试图案,记录介质和检测率计算装置的检测率计算方法
    • US20070113136A1
    • 2007-05-17
    • US11585910
    • 2006-10-25
    • Yukinori Nakajima
    • Yukinori Nakajima
    • G01R31/28G06F11/00
    • G06F17/5036G01R31/31835
    • To provide a detection rate calculation method of a test pattern for calculating how much a test pattern can detect short-out generated between the adjacent lines in an integrated circuit. A layout creating program 12 creates layout data 25 from circuit data 21, and creates the information of the adjacent lines from layout data 25 as the adjacent line information 24. A transistor level simulation program 11 executes simulation by using a test pattern 22 and creates a potential of each line in the circuit as the potential information 23. A fault detection rate calculation program 13 checks if a potential difference between the adjacent lines is not less than a predetermined potential difference or not from the adjacent line information 24 and the potential information 23 and calculates a detection rate of short-out.
    • 提供一种测试图案的检测率计算方法,用于计算测试图案可以检测集成电路中相邻行之间产生的短路的程度。 布局创建程序12从电路数据21生成布局数据25,并且从布局数据25创建相邻行的信息作为相邻行信息24。 晶体管电平仿真程序11通过使用测试图案22执行模拟,并且产生电路中的每一行的电位作为电位信息23。 故障检测率计算程序13检查相邻行之间的电位差是否不小于来自相邻行信息24和潜在信息23的预定电位差,并计算短路检测率。
    • 9. 发明授权
    • Inspection method and inspection apparatus for semiconductor integrated circuit
    • 半导体集成电路检测方法及检验装置
    • US07404158B2
    • 2008-07-22
    • US11250377
    • 2005-10-17
    • Yukinori Nakajima
    • Yukinori Nakajima
    • G06F17/50
    • G01R31/318357G06F11/261
    • In a semiconductor integrated circuit inspection method of inspecting a semiconductor integrated circuit including plural transistors according to which a test pattern generated for the semiconductor integrated circuit is input to an input terminal of the semiconductor integrated circuit, the time during which a voltage applied upon each of the transistors remains equal to or higher than a predetermined voltage is measured in response to inputting of the test pattern at the input terminal, and the ratio of thus measured time to the inspection time for the semiconductor integrated circuit is calculated. In certain example embodiments of this invention, this is advantageous in that it may be possible to verify whether a generated test pattern is preferable by grasping a state of voltage applied upon each transistor during a reliability test, so as to help maintain accuracy of reliability testing.
    • 在半导体集成电路检查方法中,检查包括多个晶体管的半导体集成电路,根据该半导体集成电路,为半导体集成电路产生的测试图案被输入到半导体集成电路的输入端, 响应于在输入端子处输入测试图案来测量晶体管保持等于或高于预定电压,并且计算这样测量的时间与半导体集成电路的检查时间的比率。 在本发明的某些示例实施例中,这是有利的,因为通过在可靠性测试期间通过掌握施加在每个晶体管上的电压的状态来验证产生的测试图案是否是优选的,以便有助于保持可靠性测试的准确性 。