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    • 8. 发明授权
    • Semiconductor device fabrication method
    • 半导体器件制造方法
    • US07030026B2
    • 2006-04-18
    • US10695874
    • 2003-10-30
    • Yuka HayamiJunji OhTakashi SaikiMasataka Kase
    • Yuka HayamiJunji OhTakashi SaikiMasataka Kase
    • H01L21/302
    • H01L21/31133H01L21/31138H01L21/823814H01L29/665
    • The semiconductor device fabrication method comprises the step of forming electrodes 20 in a first element region 14n and in a second element region 14p; the step of forming a first resist film 22 which is opened in the first element region 14n; the step of forming a first dopant diffused region 28 with the first resist film 22 and the gate electrode 20 as a mask; the first ashing processing step of ashing the first resist film 22; the step of forming a sidewall insulation film 42 over the side wall of the gate electrode 20; the step of forming a second resist film 44 which is opened in the first element region 14n; the forming a second dopant diffused region 48 with the second resist film 44, the gate electrode 20 and the sidewall insulation film 42 as a mask; and the second ashing processing step for ashing the second resist film 44. The ashing processing period of time in the first ashing processing step is shorter than the ashing processing period of time in the second ashing processing step.
    • 半导体器件制造方法包括在第一元件区域14n和第二元件区域14p中形成电极20的步骤; 形成在第一元件区域14n中打开的第一抗蚀剂膜22的步骤; 以第一抗蚀剂膜22和栅电极20为掩模形成第一掺杂剂扩散区域28的步骤; 灰化第一抗蚀剂膜22的第一灰化处理步骤; 在栅电极20的侧壁上形成侧壁绝缘膜42的步骤; 形成在第一元件区域14n中打开的第二抗蚀剂膜44的步骤; 以第二抗蚀剂膜44,栅极电极20和侧壁绝缘膜42为掩模形成第二掺杂剂扩散区域48; 以及用于灰化第二抗蚀剂膜44的第二灰化处理步骤。 第一灰化处理步骤中的灰化处理时间段比第二灰化处理步骤中的灰化处理时间段短。