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    • 1. 发明授权
    • Energy harvester for converting motion to electricity using one or more multiple degree of freedom pendulums
    • 能量收集器,用于使用一个或多个多自由度摆动将动作转换为电力
    • US09520758B1
    • 2016-12-13
    • US15164875
    • 2016-05-26
    • Patrick XuRun De ZhuYu Qing LiuEthan HuBocheng Cai
    • Patrick XuRun De ZhuYu Qing LiuEthan HuBocheng Cai
    • H02K7/10H02K7/18F03G7/08
    • H02K7/1853F03G7/08
    • An energy harvester system (EHS) for converting a multiple degree of freedom (MDF) pendulum motion into a rotational motion is provided. The EHS includes a pendulum, a pointing element, and motion control slots (MCSs) enclosed in an external housing. Ambient motion from the external housing generates a MDF pendulum motion in the pendulum. The pointing element is slidably positioned on a rod of the pendulum. The MCSs receive a connector that connects the pointing element to the rod of the pendulum and allow the connector to traverse the MCSs, thereby controlling slidable movement of the pointing element along with the pendulum. When the pendulum moves to first ends of the MCSs, the pointing element slides on the rod to allow a pointer of the pointing element to contact and rotate a gear, thereby converting the MDF pendulum motion into a rotational motion of the gear, which drives an electric generator.
    • 提供了一种用于将多自由度(MDF)摆动转换为旋转运动的能量收集器系统(EHS)。 EHS包括摆放在外壳中的摆锤,指向元件和运动控制槽(MCS)。 来自外壳的环境运动在钟摆中产生MDF摆动。 指向元件可滑动地定位在摆锤的杆上。 MCS接收连接器,该连接器将指向元件连接到摆锤杆上,并允许连接器穿过MCS,从而控制指示元件与摆锤的滑动运动。 当摆动移动到MCS的第一端时,指向元件在杆上滑动以允许指示元件的指针接触并旋转齿轮,从而将MDF摆动运动转换成齿轮的旋转运动,其驱动 发电机
    • 3. 发明授权
    • Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state
    • 小而高功效的缓存,可在处理器处于低功耗状态时为背景DMA设备提供数据
    • US07958312B2
    • 2011-06-07
    • US11559069
    • 2006-11-13
    • Laurent R. MollYu Qing ChengPeter N. GlaskowskySeungyoon Peter Song
    • Laurent R. MollYu Qing ChengPeter N. GlaskowskySeungyoon Peter Song
    • G06F12/00
    • G06F12/0835G06F1/3225G06F12/0802G06F12/0808G06F12/0864G06F12/0888G06F2212/1028G06F2212/6046Y02D10/13
    • Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).
    • 当微处理器中的缓存数据由于任何或所有微处理器处于低电平状态时,微处理器中的高速缓存数据不可访问时,小型和功率高效的缓冲器/微型高速缓冲存储器源和接收器被选择指向微处理器的相干域中的存储器空间, 电源状态不支持窥探。 通过缓冲器/微型缓存来满足所选择的DMA访问通过允许微处理器(或其一部分)保持在低功率状态来降低功耗。 缓冲器/微型高速缓存可以相对于微处理器中的高速缓存数据非相干地操作(暂时地),并且在微处理器(或其部分)转换到启用窥探的高功率状态之前,在去激活之前刷新以与缓存的数据同步 。 或者,缓冲器/微型缓存可以以与缓存的数据相一致的方式(递增地)操作。 微处理器实现具有相关联的高速缓存系统(例如第一,第二和更高级别高速缓存的各种布置)的一个或多个处理器。
    • 4. 发明授权
    • Power conservation via DRAM access reduction
    • 通过DRAM访问减少节电
    • US07904659B2
    • 2011-03-08
    • US11559133
    • 2006-11-13
    • Laurent R. MollYu Qing ChengPeter N. GlaskowskySeungyoon Peter Song
    • Laurent R. MollYu Qing ChengPeter N. GlaskowskySeungyoon Peter Song
    • G06F12/00
    • G06F12/0802G06F1/3203G06F1/3225G06F1/3275G06F12/0875G06F12/0888G06F13/1694G06F2212/1028G06F2212/2515Y02D10/13Y02D10/14
    • Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.
    • 通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。 在缓冲模式下,当CPU开始在低功耗状态下运行时,与缓存/微型缓存进行匹配的非缓存访问(例如由DMA设备产生的)与指定的物理地址范围匹配,而不是由存储器控制器 和DRAM。 缓冲/微型缓存处理包括在引用未命中时分配线路,以及当引用命中时从缓冲器/微型缓存器返回缓存数据。 根据多个替换策略中的一个替换策略,在缓冲器/微型缓存中替换行,包括当没有可用的空行时停止替换。 在正常模式下,当CPU开始在高功率状态下运行时,缓冲器/微型缓存类似于常规高速缓存,并且不能处理非缓存访问。 在一种使用场景中,保留在缓冲/微型缓存中的数据是以压缩格式维护的图形刷新数据。
    • 5. 发明授权
    • Power conservation via DRAM access
    • 通过DRAM访问进行节能
    • US07899990B2
    • 2011-03-01
    • US11559192
    • 2006-11-13
    • Laurent R. MollSeungyoon Peter SongPeter N. GlaskowskyYu Qing Cheng
    • Laurent R. MollSeungyoon Peter SongPeter N. GlaskowskyYu Qing Cheng
    • G06F13/00
    • G06F1/3203G06F1/3225G06F1/3275G06F12/0802G06F12/0888G06F2212/2515Y02D10/13Y02D10/14
    • Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.
    • 通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。 在缓冲模式下,当CPU开始在低功率状态下运行时,与缓存/存储器相关的特定物理地址范围匹配或具有访问本身的特定特性的非缓存访问(例如由DMA设备生成) 微型缓存,而不是由存储器控制器和DRAM。 缓冲/微型缓存处理包括在引用未命中时分配线路,以及当引用命中时从缓冲器/微型缓存器返回缓存数据。 根据多个替换策略中的一个替换策略,在缓冲器/微型缓存中替换行,包括当没有可用的空行时停止替换。 在正常模式下,当CPU开始在高功率状态下运行时,缓冲器/微型缓存类似于常规高速缓存,并且不能处理非缓存访问。
    • 7. 发明授权
    • Delta-sigma modulators with improved noise performance
    • 具有改进噪声性能的Delta-Σ调制器
    • US06670902B1
    • 2003-12-30
    • US10162324
    • 2002-06-04
    • John Laurence MelansonYu Qing Yang
    • John Laurence MelansonYu Qing Yang
    • H03M300
    • H03M3/368H03M3/424H03M3/452
    • An integrator stage for use in a delta sigma modulator includes an operational amplifier, an integration capacitor coupling an output of the operational amplifier and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors having first plates coupled electrically in common at a common plate node and switching circuitry for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch for selectively coupling the common plate node and the summing node during an integration phase.
    • 用于Δ-Σ调制器的积分器级包括运算放大器,耦合运算放大器的输出的积分电容器和运算放大器输入端的求和节点和反馈路径。 反馈路径包括第一和第二电容器,该第一和第二电容器具有在公共板节点处共同电耦合的第一板和用于在采样阶段期间将选定的参考电压采样到电容器的第二板上的开关电路。 积分器级还包括用于在积分阶段期间选​​择性地耦合公共板节点和求和节点的开关。
    • 10. 发明申请
    • DIFFUSION TENSOR MAGNETIC RESONANCE IMAGING METHOD
    • 扩散传感器磁共振成像方法
    • US20130338486A1
    • 2013-12-19
    • US13917895
    • 2013-06-14
    • Yu Qing Huang
    • Yu Qing Huang
    • G01R33/563
    • G01R33/56341G01R33/5676
    • In a diffusion tensor magnetic resonance imaging method for imaging a myocardial fiber structure, the diaphragm position of a subject is detected and a determination is made as to whether the diaphragm position of the subject falls into the acceptance region or not. If it does not, continue the diaphragm position of the examination subject is continued to be detected. If and when the diaphragm position is in the acceptance region, an echo planar imaging sequence with stimulated echo is executed with two electrocardiogram triggers, so as to acquire diffusion tensor image data of the myocardial fiber structure. The cardiac DTI image data thus can be obtained under free respiration of the subject, and the influence of respiratory movement is reduced and the scanning time is shortened.
    • 在用于对心肌纤维结构进行成像的扩散张量磁共振成像方法中,检测被检体的膜片位置,并且确定被检体的隔膜位置是否落入接受区域。 如果没有,继续检查检查对象的隔膜位置。 如果当隔膜位置在接受区域中时,用两个心电图触发器执行具有受激回波的回波平面成像序列,以获得心肌纤维结构的扩散张量图像数据。 因此,可以在受试者的自由呼吸下获得心脏DTI图像数据,并且减少呼吸运动的影响并缩短扫描时间。