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    • 7. 发明授权
    • Nonvolatile semiconductor memory system having first and second error correction units
    • 具有第一和第二误差校正单元的非易失性半导体存储器系统
    • US08572465B2
    • 2013-10-29
    • US12848476
    • 2010-08-02
    • Hironori UchikawaYoshihisa Kondo
    • Hironori UchikawaYoshihisa Kondo
    • G06F11/00
    • G06F11/10H03M13/05Y02D10/13
    • A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.
    • 非易失性半导体存储器系统包括半导体存储器,至少一个第一纠错单元和至少一个第二纠错单元。 半导体存储器存储用LDPC码编码的数据帧。 所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。 所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。 所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。
    • 10. 发明授权
    • Semiconductor storage device equipped with a sense amplifier for reading data and threshold-voltage-information data
    • 配备有用于读取数据的读出放大器和阈值电压信息数据的半导体存储装置
    • US08036034B2
    • 2011-10-11
    • US12564425
    • 2009-09-22
    • Hitoshi ShigaYoshihisa Kondo
    • Hitoshi ShigaYoshihisa Kondo
    • G11C16/26
    • G11C11/5642G11C16/0483G11C16/3418G11C29/00
    • A semiconductor storage device comprises: a sense amplifier circuit; a first data retaining circuit and a second data retaining circuit configured to retain data and threshold voltage information, the second data retaining circuit output the data and the threshold voltage information to the outside; and a control circuit configured to control operation. The sense amplifier circuit is configured to perform a data-read operation and a threshold-voltage-information read operation at the same time. The control circuit is configured to control read operations so that either one of the data or the threshold voltage information for which a read operation is finished earlier is output from the second data retaining circuit, and the other one of the data or the threshold voltage information for which a read operation is not finished yet is read from a memory cell array and retained in the first data retaining circuit.
    • 半导体存储装置包括:读出放大器电路; 第一数据保持电路和第二数据保持电路,被配置为保持数据和阈值电压信息,第二数据保持电路将数据和阈值电压信息输出到外部; 以及控制电路,被配置为控制操作。 感测放大器电路被配置为同时执行数据读取操作和阈值电压信息读取操作。 控制电路被配置为控制读取操作,使得先前完成读取操作的数据或阈值电压信息中的任何一个从第二数据保持电路输出,另一个数据或阈值电压信息 读取操作尚未完成,从存储单元阵列中读出并保留在第一数据保持电路中。