专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060049507A1 Semiconductor device and wire bonding chip size package therefor 失效
标题翻译：半导体器件和引线接合芯片尺寸封装
公开(公告)号：US20060049507A1
公开(公告)日：2006-03-09
申请号：US11214983
申请日：2005-08-31
申请人： Yoshihiro Ohkura
发明人： Yoshihiro Ohkura
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/48 , H01L23/3114 , H01L23/525 , H01L24/45 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/4813 , H01L2224/48464 , H01L2224/48599 , H01L2224/48699 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/20752 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device incorporated in a wire bonding chip size package (WBCSP) is designed such that a plurality of pads are formed on the surface of a semiconductor substrate and are connected to external terminals via conductive posts, wherein first and second rewiring patterns are respectively connected to the pads. All elements are sealed within an insulating layer such that the external terminals are partially exposed on the surface, wherein an uppermost portion of a conductive wire is positioned above the rewiring patterns and is also positioned below the lower ends of the external terminals. This realizes short wiring distances between the pads and the external terminals; hence, it is possible to reduce the wiring resistance and wiring delay time; it is possible to increase a freedom of degree regarding wiring without causing short-circuit failure; and, it is possible to easily change the wiring in a short period of time.
摘要翻译：结合在引线接合芯片尺寸封装（WBCSP）中的半导体器件被设计成使得多个焊盘形成在半导体衬底的表面上并且经由导电柱连接到外部端子，其中第一和第二重新布线图案分别连接到垫子所有元件被密封在绝缘层内，使得外部端子部分地暴露在表面上，其中导线的最上部分位于重新布线图案上方并且也位于外部端子的下端之下。这实现了焊盘和外部端子之间的短布线距离; 因此，可以降低布线电阻和布线延迟时间; 可以在不引起短路故障的情况下增加布线的自由度; 并且可以在短时间内容易地改变配线。

2. 发明授权

US08224062B2 Method and apparatus for inspection of wafer and semiconductor device 有权
标题翻译：晶圆和半导体器件检验方法及装置
公开(公告)号：US08224062B2
公开(公告)日：2012-07-17
申请号：US11837261
申请日：2007-08-10
申请人： Yoshihiro Ohkura , Yoshio Fukuda
发明人： Yoshihiro Ohkura , Yoshio Fukuda
IPC分类号： G06K9/62
CPC分类号： G01N21/9501 , G01N21/9505
摘要： An individually isolated wafer adapted to a semiconductor chip is subjected to inspection in which an infrared ray is irradiated onto the backside of the wafer whose surface is sealed with a resin layer such that the optical axis thereof perpendicularly or slantingly crosses the surface of the wafer, whereby an image clearly showing cracks formed in the wafer is produced based on the reflected ray. Before or after an exterior inspection process, a tape inspection process is performed by use of an image of the surface of a dicing tape, in which a plurality of semiconductor chips are once attached onto and then separated from, so as to detect at least one of a defective element, a crack mark, and a foreign mark with regard to the semiconductor chip subjected to inspection.
摘要翻译：对半导体芯片进行单独隔离的晶片进行检查，其中将红外线照射到其表面被树脂层密封的晶片的背面，使得其光轴垂直或倾斜地穿过晶片的表面，从而基于反射光线产生清楚地显示晶片中形成的裂纹的图像。在外部检查过程之前或之后，通过使用其中多个半导体芯片一旦被附着到其上并随后分离的切割带的表面的图像来进行带检查处理，以便检测至少一个缺陷元件，裂纹标记和外部标记。

3. 发明申请

US20080094094A1 APPARATUS FOR TESTING A SEMICONDUCTOR DEVICE 失效
标题翻译：用于测试半导体器件的装置
公开(公告)号：US20080094094A1
公开(公告)日：2008-04-24
申请号：US11860229
申请日：2007-09-24
申请人： YOSHIHIRO OHKURA
发明人： YOSHIHIRO OHKURA
IPC分类号： G01R31/26
CPC分类号： G01R31/2887 , G01R31/2893
摘要： An apparatus for testing a semiconductor device that has opposing first and second sides is provided. The semiconductor device includes at least one functional unit on the first side and a plurality of terminals on the second side. The apparatus may include, but is not limited to, a mounting structure, and a plurality of electrodes. The mounting structure has at least one stage that is configured to allow the semiconductor device to be mounted thereon. The mounting structure has a communicating hole that penetrates the mounting structure from the stage. The communicating hole allows the at least one functional unit to face to the communicating hole while the semiconductor device is mounted on the stage. Each of the plurality of electrodes is configured to be contactable to a corresponding one of the plurality of terminals, while the semiconductor device is mounted on the stage.
摘要翻译：提供一种用于测试具有相对的第一和第二侧面的半导体器件的装置。半导体器件包括第一侧上的至少一个功能单元和第二侧上的多个端子。该装置可以包括但不限于安装结构和多个电极。安装结构具有至少一个构造成允许半导体器件安装在其上的级。安装结构具有从工作台穿过安装结构的连通孔。连通孔允许至少一个功能单元面对连通孔，而半导体器件安装在平台上。多个电极中的每一个被配置为可以与多个端子中的相应一个端子相接触，同时半导体器件安装在平台上。

4. 发明申请

US20050199995A1 Semiconductor element and wafer level chip size package therefor 有权
标题翻译：半导体元件和晶圆级芯片尺寸封装
公开(公告)号：US20050199995A1
公开(公告)日：2005-09-15
申请号：US11076055
申请日：2005-03-10
申请人： Kentaro Nomoto , Yuki Igawa , Hiroshi Saitoh , Takashi Sato , Toshio Ohashi , Yoshihiro Ohkura
发明人： Kentaro Nomoto , Yuki Igawa , Hiroshi Saitoh , Takashi Sato , Toshio Ohashi , Yoshihiro Ohkura
IPC分类号： H01L23/12 , H01L23/34 , H01L23/48 , H01L23/50 , H01L23/52
CPC分类号： H01L24/17 , H01L23/12 , H01L23/34 , H01L23/48 , H01L23/50 , H01L23/52 , H01L2224/02377 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05548 , H01L2224/05556 , H01L2224/05559 , H01L2224/05569 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2224/14132 , H01L2224/16238 , H01L2224/81122 , H01L2224/8113 , H01L2224/81132 , H01L2924/00011 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01322 , H01L2924/10158 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/014 , H01L2924/00012 , H01L2224/81805 , H01L2924/00014
摘要： A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.
摘要翻译：封装在晶片级芯片尺寸封装（WLCSP）中的半导体器件包括形成在半导体芯片的表面上的多个焊盘电极，其中在除了焊盘电极之外的半导体芯片的表面上形成第一绝缘层; 多个连接电极和至少一个散热电极形成在第一绝缘层的表面上; 焊盘电极和连接电极经由第一布线部分相互连接; 所述散热电极与第二配线部连接，并且形成第二绝缘层以包围所述电极和布线部分，其中所述第二布线部分布置在所述半导体芯片的加热部分附近，并且形成在除了对应于所述半导体芯片的规定区域之外的所述第一绝缘层的表面上第一接线部。

5. 发明授权

US06621176B1 Input device for use in vehicles for inputting settings pertaining to driver's intention of acceleration and deceleration 有权
标题翻译：用于车辆输入与驾驶员加速和减速意图有关的设置的输入装置
公开(公告)号：US06621176B1
公开(公告)日：2003-09-16
申请号：US09649968
申请日：2000-08-28
申请人： Chikao Nagasaka , Yoshihiro Ohkura , Hiroshi Tsuge , Toru Nakamura
发明人： Chikao Nagasaka , Yoshihiro Ohkura , Hiroshi Tsuge , Toru Nakamura
IPC分类号： B60L100
CPC分类号： F16H59/0204 , B60K20/06 , B60K26/00 , B60K31/042 , F16H2059/0239 , F16H2059/0247 , Y10T74/20067
摘要： An input device for use in a vehicle for inputting settings pertaining to a driver's intention of acceleration and deceleration includes a running mode selection switch and an acceleration/deceleration switch. A plurality of modes, for example, a manual speed change mode, an automatic speed change mode, a speed setting mode, and a distance-between-cars setting mode, are selectively set in the running mode selection switch. The acceleration/deceleration switch allows an accelerating or decelerating operation in correspondence to the selected mode. Operation switches which have been conventionally provided separately for each of functions are integrated into two parts, that is, the running mode selection switch and the acceleration/deceleration switch. After a desired mode has been selected, a desired function can be realized only by operation corresponding to a driver's intention of acceleration or deceleration. Accordingly, even if the driver is not experienced in using a plurality of functions, more reasonable operation suited for human perception and reaction allows the driver to become easily accustomed to use the device.
摘要翻译：用于车辆中用于输入关于驾驶员的加速和减速意图的设置的输入装置包括行驶模式选择开关和加速/减速开关。在运行模式选择开关中选择性地设置多种模式，例如手动变速模式，自动变速模式，速度设定模式和轿厢间距离设定模式。加速/减速开关允许对应于所选模式的加速或减速操作。通常为每个功能单独提供的操作开关集成在两个部分中，即行驶模式选择开关和加速/减速开关。在选择了期望的模式之后，可以仅通过对应于驾驶员的加速或减速的意图的操作来实现期望的功能。因此，即使驾驶员在使用多种功能方面没有经验，适合于人的感知和反应的更合理的操作使驾驶员变得容易地习惯使用该装置。

6. 发明授权

US07830011B2 Semiconductor element and wafer level chip size package therefor 有权
标题翻译：半导体元件和晶圆级芯片尺寸封装
公开(公告)号：US07830011B2
公开(公告)日：2010-11-09
申请号：US11076055
申请日：2005-03-10
申请人： Kentaro Nomoto , Yuki Igawa , Hiroshi Saitoh , Takashi Sato , Toshio Ohashi , Yoshihiro Ohkura
发明人： Kentaro Nomoto , Yuki Igawa , Hiroshi Saitoh , Takashi Sato , Toshio Ohashi , Yoshihiro Ohkura
IPC分类号： H01L23/48
CPC分类号： H01L24/17 , H01L23/12 , H01L23/34 , H01L23/48 , H01L23/50 , H01L23/52 , H01L2224/02377 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05171 , H01L2224/05548 , H01L2224/05556 , H01L2224/05559 , H01L2224/05569 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/13 , H01L2224/13022 , H01L2224/13023 , H01L2224/131 , H01L2224/14132 , H01L2224/16238 , H01L2224/81122 , H01L2224/8113 , H01L2224/81132 , H01L2924/00011 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01322 , H01L2924/10158 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/014 , H01L2924/00012 , H01L2224/81805 , H01L2924/00014
摘要： A semiconductor device, encapsulated in a wafer level chip size package (WLCSP), includes a plurality of pad electrodes formed on the surface of a semiconductor chip, wherein a first insulating layer is formed on the surface of the semiconductor chip except the pad electrodes; a plurality of connection electrodes and at least one heat-dissipation electrode are formed on the surface of the first insulating layer; the pad electrodes and the connection electrodes are mutually connected via a first wiring portion; the heat-dissipation electrode is connected with a second wiring portion; and a second insulating layer is formed to enclose the electrodes and wiring portions, wherein the second wiring portion is arranged in proximity to a heating portion of the semiconductor chip and is formed on the surface of the first insulating layer except the prescribed region corresponding to the first wiring portion.
摘要翻译：封装在晶片级芯片尺寸封装（WLCSP）中的半导体器件包括形成在半导体芯片的表面上的多个焊盘电极，其中在除了焊盘电极之外的半导体芯片的表面上形成第一绝缘层; 多个连接电极和至少一个散热电极形成在第一绝缘层的表面上; 焊盘电极和连接电极经由第一布线部分相互连接; 所述散热电极与第二配线部连接，并且形成第二绝缘层以包围所述电极和布线部分，其中所述第二布线部分布置在所述半导体芯片的加热部分附近，并且形成在除了对应于所述半导体芯片的规定区域之外的所述第一绝缘层的表面上第一接线部。

7. 发明申请

US20080037859A1 METHOD AND APPARATUS FOR INSPECTION OF WAFER AND SEMICONDUCTOR DEVICE 有权
标题翻译：用于检查波形和半导体器件的方法和装置
公开(公告)号：US20080037859A1
公开(公告)日：2008-02-14
申请号：US11837261
申请日：2007-08-10
申请人： YOSHIHIRO OHKURA , YOSHIO FUKUDA
发明人： YOSHIHIRO OHKURA , YOSHIO FUKUDA
IPC分类号： G06K9/00 , G01N21/88
CPC分类号： G01N21/9501 , G01N21/9505
摘要： An individually isolated wafer adapted to a semiconductor chip is subjected to inspection in which an infrared ray is irradiated onto the backside of the wafer whose surface is sealed with a resin layer such that the optical axis thereof perpendicularly or slantingly crosses the surface of the wafer, whereby an image clearly showing cracks formed in lie wafer is produced based on the reflected ray. Before or after an exterior inspection process, a tape inspection process is performed by use of an image of the surface of a dicing tape, in which a plurality of semiconductor chips are once attached onto and then separated from, so as to detect at least one of a defective element, a crack mark, and a foreign mark with regard to the semiconductor chip subjected to inspection,
摘要翻译：对半导体芯片进行单独隔离的晶片进行检查，其中将红外线照射到其表面被树脂层密封的晶片的背面，使得其光轴垂直或倾斜地穿过晶片的表面，从而基于反射的光线产生清楚地显示晶片上形成的裂纹的图像。在外部检查过程之前或之后，通过使用其中多个半导体芯片一旦被附着到其上并随后分离的切割带的表面的图像来进行带检查处理，以便检测至少一个关于被检查的半导体芯片的缺陷元件，裂纹标记和外部标记，

8. 发明授权

US07642799B2 Test chip socket and method for testing a chip 失效
标题翻译：测试芯片插座和芯片测试方法
公开(公告)号：US07642799B2
公开(公告)日：2010-01-05
申请号：US11841396
申请日：2007-08-20
申请人： Yoshihiro Ohkura
发明人： Yoshihiro Ohkura
IPC分类号： G01R31/26
CPC分类号： G01R31/2886 , G01R1/0483 , G01R31/2893
摘要： A test chip socket comprises a contact block fixed to a tester substrate, a tray mounted to the contact block, the tray having a convex part for positioning test target chips to a plurality of mount positions, and a plurality of probes each of which is held by the contact block and contacts the tester substrate and the test target chip, wherein each probe contacts with a terminal of each test target chip mounted to the mounting position when the tray mounting the plurality of the test target chip is fixed to the contact block.
摘要翻译：测试芯片插座包括固定到测试器基板的接触块，安装到接触块的托盘，具有用于将测试目标芯片定位到多个安装位置的凸起部分的托盘，以及多个探针，每个探针被保持通过接触块并接触测试基板和测试目标芯片，其中当将安装多个测试目标芯片的托盘固定到接触块时，每个探针与安装到安装位置的每个测试目标芯片的端子接触。

9. 发明授权

US07388198B2 Electron microscope 有权
标题翻译：电子显微镜
公开(公告)号：US07388198B2
公开(公告)日：2008-06-17
申请号：US11191147
申请日：2005-07-27
申请人： Yoshihiro Ohkura
发明人： Yoshihiro Ohkura
IPC分类号： G21K7/00
CPC分类号： H01J37/256 , H01J2237/24455 , H01J2237/2538
摘要： An electron microscope capable of producing EELS (electron energy-loss spectroscopy) has a spectral position correcting signal supply circuit for supplying a spectral position correcting signal H to a first driver amplifier to project spectra at the center of a CCD camera. This correcting signal H corresponds to a beam deflection signal A′ supplied from a scan generator to a second driver amplifier, an excitation signal B′ supplied from an intermediate lens excitation signal supply circuit to a third driver amplifier, and another excitation signal supplied from a projector lens excitation signal supply circuit to a fourth driver amplifier.
摘要翻译：能够产生EELS（电子能量损失光谱）的电子显微镜具有光谱位置校正信号供给电路，用于将光谱位置校正信号H提供给第一驱动放大器，以在CCD照相机的中心投影光谱。该校正信号H对应于从扫描发生器向第二驱动放大器提供的光束偏转信号A'，从中间透镜激励信号供给电路提供给第三驱动放大器的激励信号B'，以及从第投影镜头激励信号供应电路到第四个驱动放大器。

10. 发明申请

US20080054925A1 TEST CHIP SOCKET 失效
标题翻译：测试芯片插座
公开(公告)号：US20080054925A1
公开(公告)日：2008-03-06
申请号：US11841396
申请日：2007-08-20
申请人： YOSHIHIRO Ohkura
发明人： YOSHIHIRO Ohkura
IPC分类号： G01R1/04 , G01R31/26
CPC分类号： G01R31/2886 , G01R1/0483 , G01R31/2893
摘要： A test chip socket comprises a contact block fixed to a tester substrate, a tray mounted to the contact block, the tray having a convex part for positioning test target chips to a plurality of mount positions, and a plurality of probes each of which is held by the contact block and contacts the tester substrate and the test target chip, wherein each probe contacts with a terminal of each test target chip mounted to the mounting position when the tray mounting the plurality of the test target chip is fixed to the contact block.
摘要翻译：测试芯片插座包括固定到测试器基板的接触块，安装到接触块的托盘，具有用于将测试目标芯片定位到多个安装位置的凸起部分的托盘，以及多个探针，每个探针被保持通过接触块并接触测试基板和测试目标芯片，其中当将安装多个测试目标芯片的托盘固定到接触块时，每个探针与安装到安装位置的每个测试目标芯片的端子接触。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式