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1. 发明申请

US20130082755A1 FILTERING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 有权
标题翻译：滤波电路和具有该电路的半导体集成电路
公开(公告)号：US20130082755A1
公开(公告)日：2013-04-04
申请号：US13302167
申请日：2011-11-22
申请人： Hye-Young LEE , Yong-Mi KIM
发明人： Hye-Young LEE , Yong-Mi KIM
IPC分类号： H03L7/06 , H03K5/00
CPC分类号： H03L7/0814 , H03K2005/00241 , H03L7/0816 , H03L7/093
摘要： A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.
摘要翻译：滤波电路包括：抖动判定基准控制部，被配置为根据操作模式确定抖动判定基准，响应抖动判定基准输出控制信号;滤波部，被配置为响应于抖动判定基准控制信号，并且响应于所设置的抖动判定参考，确定在采样周期期间是否维持输入信号。

2. 发明申请

US20130162321A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130162321A1
公开(公告)日：2013-06-27
申请号：US13446455
申请日：2012-04-13
申请人： Yong-Mi KIM
发明人： Yong-Mi KIM
IPC分类号： H03K17/16 , H03K17/00
CPC分类号： G11C7/1006 , G11C7/1057
摘要： A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.
摘要翻译：半导体器件包括：信息生成电路，被配置为生成第一信息;信息复用电路，被配置为复用第一信息和第二信息;以及信息驱动电路，被配置为响应于信息复用电路的输出信号来驱动输出焊盘。

3. 发明申请

US20130114352A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20130114352A1
公开(公告)日：2013-05-09
申请号：US13404734
申请日：2012-02-24
申请人： Yong-Mi KIM
发明人： Yong-Mi KIM
IPC分类号： G11C7/10 , G11C8/18
CPC分类号： G11C7/1039 , G11C7/222
摘要： A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.
摘要翻译：一种半导体存储器件，包括配置为响应于使能信号接收并行输入数据和输出串行数据或将管锁存电路的输出端子设置在预定电压电平的管锁存电路，以及同步电路，其被配置为输出输出管锁存电路的数据与内部时钟同步。

4. 发明申请

US20120217991A1 IMPEDANCE CONTROL CIRCUIT AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME 有权
标题翻译：阻抗控制电路和集成电路芯片，包括它们
公开(公告)号：US20120217991A1
公开(公告)日：2012-08-30
申请号：US13334022
申请日：2011-12-21
申请人： Dong-Wook JANG , Yong-Mi KIM
发明人： Dong-Wook JANG , Yong-Mi KIM
IPC分类号： H03K19/003
CPC分类号： H03K19/0005
摘要： A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code generation unit configured to generate the first impedance code so that an impedance value of the first impedance unit and an impedance value of the resistor are at a ratio of X:Y, dummy impedance units that receive the first impedance code and drive a second node with the first voltage, a second impedance unit having an impedance value based on a second impedance code and configured to drive the second node with a second voltage, and a second code generation unit configured to generate the second impedance code so that an overall impedance value of the dummy impedance units and an impedance value of the second impedance unit are at a ratio of X:Y
摘要翻译：一种电路，包括具有基于第一阻抗码的阻抗值并被配置为驱动与第一电压耦合的电阻器的第一节点的第一阻抗单元，第一代码产生单元，被配置为产生第一阻抗代码，使得阻抗第一阻抗单元的值和电阻器的阻抗值为X:Y，接收第一阻抗代码的虚拟阻抗单元和驱动具有第一电压的第二节点的比例，具有基于阻抗值的第二阻抗单元在第二阻抗代码上并被配置为以第二电压驱动第二节点，以及第二代码生成单元，被配置为生成第二阻抗代码，使得虚拟阻抗单元的总阻抗值和第二阻抗单元的阻抗值是X：Y的比例

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