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1. 发明申请

US20120231553A1 SUBSTRATE PROCESSING APPARATUS AND FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件的基板处理装置和制造工艺
公开(公告)号：US20120231553A1
公开(公告)日：2012-09-13
申请号：US13479496
申请日：2012-05-24
申请人： Yoichi OKITA , Koji IBI , Minoru Suzuki , Yuuichi Tachino
发明人： Yoichi OKITA , Koji IBI , Minoru Suzuki , Yuuichi Tachino
IPC分类号： H01L21/311 , H01L21/3065
CPC分类号： H01J37/32633 , H01J37/321 , H01J37/32623 , H01L21/32136 , H01L21/67069
摘要： A substrate processing apparatus includes a processing vessel evacuated by an evacuation system and including therein a stage for holding thereon a substrate to be processed, the processing vessel defining therein a processing space, a processing gas supply path that introduces an etching gas into the processing vessel, a plasma source that forms plasma in the processing space, and a high-frequency source connected to the stage. The processing vessel includes therein a shielding plate dividing the processing space into a first processing space part including a surface of the substrate to be processed and a second processing space part corresponding to a remaining part of the processing space, wherein the shielding plate is formed with an opening having a size larger than a size of the substrate to be processed.
摘要翻译：基板处理装置包括由排气系统抽真空的处理容器，其中包括用于保持待处理基板的台，处理容器在其中限定处理空间，将蚀刻气体引入处理容器的处理气体供给路径，在处理空间中形成等离子体的等离子体源和连接到该级的高频源。处理容器在其中包括将处理空间分成包括待处理基板的表面的第一处理空间部分和对应于处理空间的剩余部分的第二处理空间部分的屏蔽板，其中屏蔽板形成有具有比待处理的基板的尺寸大的开口。

2. 发明授权

US07595250B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07595250B2
公开(公告)日：2009-09-29
申请号：US11490252
申请日：2006-07-21
申请人： Yoichi Okita , Genichi Komuro
发明人： Yoichi Okita , Genichi Komuro
IPC分类号： H01L21/44
CPC分类号： H01L27/11502 , H01L27/0629 , H01L27/11507 , H01L28/60
摘要： There are provided the steps of forming an insulating film over a semiconductor substrate, forming sequentially a first conductive film, a dielectric film, a second conductive film on the insulating film, etching the second conductive film and the dielectric film into a first pattern shape by using a first mask, removing the first mask, and etching simultaneously the first conductive film and the second conductive film having the first pattern shape by using a second mask to form a plurality of capacitor upper electrodes made of the second conductive film and also form a plate line as a capacitor lower electrode, which is covered with the dielectric film having the first pattern shape and has a contact region, made of the first conductive film. Accordingly, a plurality of capacitors can be formed on the capacitor lower electrode with good precision.
摘要翻译：提供了在半导体基板上形成绝缘膜的步骤，在绝缘膜上依次形成第一导电膜，电介质膜，第二导电膜，通过第二导电膜和电介质膜将第二导电膜和电介质膜蚀刻成第一图案形状使用第一掩模，去除第一掩模，并且通过使用第二掩模同时蚀刻具有第一图案形状的第一导电膜和第二导电膜，以形成由第二导电膜制成的多个电容器上电极，并且还形成板线作为电容器下电极，其被具有第一图案形状的电介质膜覆盖并具有由第一导电膜制成的接触区域。因此，能够以良好的精度在电容器下电极上形成多个电容器。

3. 发明授权

US07550799B2 Semiconductor device and fabrication method of a semiconductor device 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US07550799B2
公开(公告)日：2009-06-23
申请号：US11032628
申请日：2005-01-11
申请人： Yoichi Okita
发明人： Yoichi Okita
IPC分类号： H01L29/76
CPC分类号： H01L27/11502 , H01L21/76829 , H01L21/7687 , H01L27/11507 , H01L28/55 , H01L28/57 , H01L28/65 , H01L28/75
摘要： In a conventional semiconductor device provided with a conventional stacked type ferroelectric capacitor, there has been caused a problem of capacitor degradation by leakage between an upper electrode and a lower electrode via an etching reside, when the efficiency of utilization of a surface area is increased by decreasing the interval between the capacitors in the in-plane direction of the substrate, as a result of the one-step annealing of the laminated from of lower electrode film/ferroelectric film/upper electrode film.The present invention prevents leakage caused by short circuit between the lower electrode and the upper electrode, by forming plural lower electrodes, forming a ferroelectric film so as to cover the surface and sidewall surface of the lower electrodes and forming an upper electrode on the ferroelectric film so as to oppose with the lower electrodes. Further, as a result of forming the ferroelectric film so as to cover the lower electrodes continuously and by setting the interval between the lower electrodes and the thickness of the ferroelectric film to satisfy a predetermined relationship, the surface of the ferroelectric film is planarized and exposure of the sidewall is suppressed. Thereby, degradation of the capacitor is prevented.
摘要翻译：在具有常规堆叠型铁电电容器的常规半导体器件中，当通过蚀刻存在上电极和下电极之间的漏电的电容器劣化的问题，当表面积的利用效率增加时作为从下电极膜/铁电体膜/上电极膜层叠的一步退火的结果，减小了基板的面内方向的电容器间的间隔。本发明通过形成多个下电极来防止由下部电极和上部电极之间的短路引起的泄漏，形成铁电体膜以覆盖下部电极的表面和侧壁表面，并在铁电体膜上形成上部电极以便与下电极相对。此外，作为形成强电介质膜以便连续地覆盖下电极并且通过将下电极之间的间隔和铁电体膜的厚度设定为满足预定关系的结果，铁电膜的表面被平坦化并且曝光的侧壁被抑制。由此，能够防止电容器的劣化。

4. 发明申请

US20050153463A1 Method for fabricating ferroelectric capacitor 有权
标题翻译：铁电电容器的制造方法
公开(公告)号：US20050153463A1
公开(公告)日：2005-07-14
申请号：US11071461
申请日：2005-03-04
申请人： Yoichi Okita
发明人： Yoichi Okita
IPC分类号： H01L21/02 , H01L21/033 , H01L21/3213 , H01L21/8246 , H01L27/105 , H01L27/115 , H01L21/00
CPC分类号： H01L21/32139 , H01L21/0334 , H01L21/32136 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A method for fabricating a ferroelectric memory having memory cells arranged in arrays, wherein an Al2O3 film (2), a Pt film (3), a PZT film (4) and IrO2 film (5) are formed on an interlayer insulation film. At the time of forming a top electrode, the IrO2 film (5) is patterned using a resist mask having a part extending in the row direction, and then patterned using a resist mask having a part extending in the column direction. Consequently, a top electrode of the IrO2 film (5) having a rectangular plan view is formed at the intersection of these resist masks.
摘要翻译：一种用于制造具有排列成阵列的存储单元的铁电存储器的方法，其中Al 2 O 3膜（2），Pt膜（3），PZT膜（ 4）和IrO 2膜（5）形成在层间绝缘膜上。在形成顶部电极时，使用具有沿行方向延伸的部分的抗蚀剂掩模对IrO 2膜（5）进行构图，然后使用具有部分延伸的部分的抗蚀剂掩模列方向。因此，在这些抗蚀剂掩模的交叉处形成具有矩形平面图的IrO 2膜（5）的顶部电极。

5. 发明申请

US20050098815A1 LASER HAVING ACTIVE REGION FORMED ABOVE SUBSTRATE 有权
标题翻译：具有形成上层活性区的激光
公开(公告)号：US20050098815A1
公开(公告)日：2005-05-12
申请号：US10351336
申请日：2003-01-27
申请人： Yoichi Okita , Genichi Komuro
发明人： Yoichi Okita , Genichi Komuro
IPC分类号： H01L27/105 , H01L21/02 , H01L21/8246 , H01L27/06 , H01L27/115 , H01L21/8242 , H01L27/108 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11502 , H01L27/0629 , H01L27/11507 , H01L28/60
摘要： There are provided the steps of forming an insulating film over a semiconductor substrate, forming sequentially a first conductive film, a dielectric film, a second conductive film on the insulating film, etching the second conductive film and the dielectric film into a first pattern shape by using a first mask, removing the first mask, and etching simultaneously the first conductive film and the second conductive film having the first pattern shape by using a second mask to form a plurality of capacitor upper electrodes made of the second conductive film and also form a plate line as a capacitor lower electrode, which is covered with the dielectric film having the first pattern shape and has a contact region, made of the first conductive film. Accordingly, a plurality of capacitors can be formed on the capacitor lower electrode with good precision.
摘要翻译：提供了在半导体基板上形成绝缘膜的步骤，在绝缘膜上依次形成第一导电膜，电介质膜，第二导电膜，通过第二导电膜和电介质膜将第二导电膜和电介质膜蚀刻成第一图案形状使用第一掩模，去除第一掩模，并且通过使用第二掩模同时蚀刻具有第一图案形状的第一导电膜和第二导电膜，以形成由第二导电膜制成的多个电容器上电极，并且还形成板线作为电容器下电极，其被具有第一图案形状的电介质膜覆盖并具有由第一导电膜制成的接触区域。因此，能够以良好的精度在电容器下电极上形成多个电容器。

6. 发明授权

US06720600B2 FeRam semiconductor device with improved contact plug structure 有权
标题翻译： FeRam半导体器件具有改进的接触插塞结构
公开(公告)号：US06720600B2
公开(公告)日：2004-04-13
申请号：US10269060
申请日：2002-10-11
申请人： Yoichi Okita
发明人： Yoichi Okita
IPC分类号： H01L31119
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： There is provided a semiconductor device having a ferroelectric capacitor, which comprises capacitor protection films for covering an upper surface and a side surface the ferroelectric capacitor that is formed on a first insulating film, a hole formed in a second insulating film, which is formed on the capacitor protection films and the first insulating film, to be positioned adjacently to the side surface of the ferroelectric capacitor via the capacitor protection films, and a conductive plug formed in the hole. Accordingly, alignment margin of the contact hole to be formed next to the capacitor can be reduced.
摘要翻译：提供了一种具有铁电电容器的半导体器件，其包括用于覆盖形成在第一绝缘膜上的铁电电容器的上表面和侧表面的电容器保护膜，形成在第二绝缘膜上的孔，其形成在电容器保护膜和第一绝缘膜通过电容器保护膜与铁电电容器的侧表面相邻并且形成在孔中的导电插塞。因此，可以减少形成在电容器旁边的接触孔的对准余量。

7. 发明授权

US07198960B2 Method for fabricating ferroelectric capacitor 有权
标题翻译：铁电电容器的制造方法
公开(公告)号：US07198960B2
公开(公告)日：2007-04-03
申请号：US11071461
申请日：2005-03-04
申请人： Yoichi Okita
发明人： Yoichi Okita
IPC分类号： H01L21/00
CPC分类号： H01L21/32139 , H01L21/0334 , H01L21/32136 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A method for fabricating a ferroelectric memory having memory cells arranged in arrays, wherein an Al2O3 film (2), a Pt film (3), a PZT film (4) and IrO2 film (5) are formed on an interlayer insulation film. At the time of forming a top electrode, the IrO2 film (5) is patterned using a resist mask having a part extending in the row direction, and then patterned using a resist mask having a part extending in the column direction. Consequently, a top electrode of the IrO2 film (5) having a rectangular plan view is formed at the intersection of these resist masks.
摘要翻译：一种用于制造具有排列成阵列的存储单元的铁电存储器的方法，其中Al 2 O 3膜（2），Pt膜（3），PZT膜（ 4）和IrO 2膜（5）形成在层间绝缘膜上。在形成顶部电极时，使用具有沿行方向延伸的部分的抗蚀剂掩模对IrO 2膜（5）进行构图，然后使用具有部分延伸的部分的抗蚀剂掩模列方向。因此，在这些抗蚀剂掩模的交叉处形成具有矩形平面图的IrO 2膜（5）的顶部电极。

8. 发明申请

US20050136554A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050136554A1
公开(公告)日：2005-06-23
申请号：US10835311
申请日：2004-04-30
申请人： Yoichi Okita , Junichi Watanabe , Naoya Sashida
发明人： Yoichi Okita , Junichi Watanabe , Naoya Sashida
IPC分类号： H01L27/105 , H01L21/00 , H01L21/02 , H01L21/326 , H01L21/479 , H01L21/82 , H01L21/8246
CPC分类号： H01L28/57 , H01L27/11507
摘要： An Al2O3 film for covering a ferroelectric capacitor is formed by a sputtering process. The thickness of the Al2O3 film is preferably optimized according to amount of remanent polarization and fatigue tolerance required for the ferroelectric capacitor, for example, 10 nm to 100 nm. Next, oxygen is supplied to a PZT film via the Al203 film by executing a heat treatment in an oxygen atmosphere. As a result, an oxygen deficit in the PZT film is made up for. At this time, evaporation of Pb in the PZT film is suppressed because of the Al2O3 film, and deterioration of the fatigue tolerance responsive to decrease of Pb amount is suppressed. Subsequently, another Al2O3 film is formed as a second protective film by the sputtering process for opposing the deterioration factor in later process. The thickness of the Al2O3 film is preferably the thickness which sufficiently protects the ferroelectric capacitor from the deterioration factor in later wiring process.
摘要翻译：通过溅射法形成用于覆盖铁电电容器的Al 2 O 3 N 3膜。 Al 2 O 3膜的厚度优选根据强电介质电容器所需的剩余极化和耐疲劳性的量优化，例如10nm至100nm。接着，通过在氧气氛中进行热处理，通过Al 2 O 3膜将氧气供给到PZT膜。结果，PZT膜中的氧气缺乏。此时，由于Al 2 O 3 O 3膜，PZT膜中的Pb的蒸发被抑制，并且抑制了响应于Pb量降低的疲劳强度的劣化。随后，通过溅射工艺形成另一个Al 2 O 3 3膜作为第二保护膜，用于与稍后的工艺中的劣化因子相反。 Al 2 O 3膜的厚度优选是在稍后的布线工艺中充分保护铁电电容器免受劣化因素的厚度。

9. 发明授权

US08044447B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08044447B2
公开(公告)日：2011-10-25
申请号：US12031193
申请日：2008-02-14
申请人： Yoichi Okita , Genichi Komuro
发明人： Yoichi Okita , Genichi Komuro
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L27/11502 , H01L21/76877 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： There is provided a semiconductor device including a silicon substrate, a source/drain region formed in a surface layer of the silicon substrate, a first insulating film provided with a first hole on the first source/drain region, a conductive film formed on an inner surface of the first hole, a filler body, which is formed with a thickness to fill the first hole on the first conductive film, forms a first conduct plug together with the conductive film, and is formed of an insulating material with an upper surface being amorphous, and a capacitor, which is formed on the first contact plug and is provided with a lower electrode electrically connected to the conductive film, a capacitor dielectric film formed of a ferroelectric material, and an upper electrode.
摘要翻译：提供了一种半导体器件，包括硅衬底，形成在硅衬底的表面层中的源极/漏极区域，在第一源极/漏极区域上设置有第一孔的第一绝缘膜，形成在内部的导电膜第一孔的表面，形成有填充第一导电膜上的第一孔的厚度的填充体与导电膜一起形成第一导电栓，并且由绝缘材料形成，上表面为非晶体和电容器，其形成在第一接触插塞上并且设置有电连接到导电膜的下电极，由铁电体材料形成的电容器电介质膜和上电极。

10. 发明申请

US20100144104A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100144104A1
公开(公告)日：2010-06-10
申请号：US12708770
申请日：2010-02-19
申请人： Yoichi OKITA
发明人： Yoichi OKITA
IPC分类号： H01L21/336 , H01L21/768
CPC分类号： H01L21/76885 , B82Y10/00 , H01L21/324 , H01L21/76838 , H01L21/76879 , H01L23/5226 , H01L23/53276 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/843 , Y10S977/844 , Y10S977/938 , H01L2924/00
摘要： A plurality of origin patterns (3) containing a metal catalyst are formed over a semiconductor substrate (1). Next, an insulating film (4) covering the origin patterns (3) is formed. Next, a trench allowing at the both ends thereof the side faces of the origin patterns (3) to expose is formed. Thereafter, a wiring is formed by allowing carbon nanotubes (5) having a conductive chirality to grow in the trench. Thereafter, an insulating film covering the carbon nanotubes (5) is formed.
摘要翻译：在半导体衬底（1）上形成多个含有金属催化剂的原点图案（3）。接下来，形成覆盖原点图案（3）的绝缘膜（4）。接下来，形成在其两端处允许原点图案（3）的侧面露出的沟槽。此后，通过使具有导电手性的碳纳米管（5）在沟槽中生长来形成布线。此后，形成覆盖碳纳米管（5）的绝缘膜。

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