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1. 发明授权

US07349506B2 Semiconductor integrated circuit and method for testing the same 失效
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US07349506B2
公开(公告)日：2008-03-25
申请号：US10901165
申请日：2004-07-29
申请人： Yasushi Shizuki
发明人： Yasushi Shizuki
IPC分类号： H04B1/10
CPC分类号： G01R31/31716
摘要： A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test. The receiver capable of executing control so as to make a phase of the input data coincide with that of a recovery clock.
摘要翻译：一种方法和半导体集成电路，其中接收器接收接收数据，并且基于从PLL提供的时钟信号和接收并行传输数据的发送器执行接收处理，并且基于时钟信号执行串行传输处理;以及具有将从发射机输出的数据提供给接收机以进行测试的回送功能。能够执行控制以使输入数据的相位与恢复时钟的相位一致的接收器。

2. 发明申请

US20050201500A1 Semiconductor integrated circuit and method for testing the same 失效
公开(公告)号：US20050201500A1
公开(公告)日：2005-09-15
申请号：US10901165
申请日：2004-07-29
申请人： Yasushi Shizuki
发明人： Yasushi Shizuki
IPC分类号： G01R31/28 , G01R31/317 , H01L21/822 , H01L27/04 , H03K5/26 , H04B1/10 , H04L7/033
CPC分类号： G01R31/31716
摘要： According to the present invention, there is provided a semiconductor integrated circuit having a receiver which receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test, the receiver, as a CDR circuit, executing control so as to make the phase of the input data coincide with that of the recovery clock by a negative feedback loop having a phase comparator which receives input data and a recovery clock, compares a phase of the input data with that of the recovery clock, and outputs recovery data and a phase comparison result in a serial form, a serial/parallel conversion circuit which receives the phase comparison result, or the phase comparison result and the recovery data from the phase comparator, executes serial/parallel conversion, and outputs the phase comparison result in a parallel form, a digital filer which receives the phase comparison result from the serial/parallel conversion circuit, executes averaging processing for the phase comparison result in a predetermined period, and outputs the phase comparison result, a control circuit which receives the phase comparison result from the digital filer and outputs a control signal to control the phase of the recovery clock, and a phase interpolator which receives the clock signal and generates the recovery clock on the basis of the control signal, and the CDR circuit including a signal output circuit which inputs, to one of the control circuit and the digital filer, a signal to forcibly shift the phase of the recovery data in the negative feedback loop by a predetermined amount, a first counter which counts the number of pulses of the signal output from the signal output circuit in a predetermined period and outputs a first count value, a second counter which counts the number of pulses of the phase comparison result, which has undergone the averaging processing and is output from the digital filer, and outputs a second count value, and a signal processing circuit which receives the first count value and the second count value and compares the first count value with the second count value to determine presence/absence of a capability for absorbing the phase shift generated by the signal.

3. 发明授权

US06801071B1 Semiconductor integrated circuit device with differential output driver circuit, and system for semiconductor integrated circuit device 失效
标题翻译：具有差分输出驱动电路的半导体集成电路器件，以及用于半导体集成电路器件的系统
公开(公告)号：US06801071B1
公开(公告)日：2004-10-05
申请号：US10620382
申请日：2003-07-17
申请人： Yasushi Shizuki
发明人： Yasushi Shizuki
IPC分类号： H03K1716
CPC分类号： H03K19/00323 , H04L25/0272
摘要： A semiconductor integrated circuit device includes a differential output driver circuit arranged at each I/O portion, and a delay element. The differential output driver circuit receives a pair of differential signals generated by a circuit on the input stage. An output signal from the differential output driver circuit is transmitted through the first and second signal lines. Each of the first and second signal lines includes a global interconnection, bump, and transmission line. The delay element is inserted in at least one of the first and second signal lines. The delay element delays signals passing through the signal lines so as to make the delays of the signals substantially equal to each other, compensating for the signal delay time generated by the line length difference.
摘要翻译：半导体集成电路器件包括布置在每个I / O部分的差分输出驱动器电路和延迟元件。差分输出驱动电路接收由输入级上的电路产生的一对差分信号。来自差分输出驱动电路的输出信号通过第一和第二信号线传输。第一和第二信号线中的每一个包括全局互连，凸起和传输线。延迟元件插入第一和第二信号线中的至少一个。延迟元件延迟通过信号线的信号，使得信号的延迟基本相等，补偿由线长差产生的信号延迟时间。

4. 发明授权

US6130483A MMIC module using flip-chip mounting 失效
标题翻译： MMIC模块采用倒装芯片安装
公开(公告)号：US6130483A
公开(公告)日：2000-10-10
申请号：US35298
申请日：1998-03-05
申请人： Yasushi Shizuki , Mitsuo Konno
发明人： Yasushi Shizuki , Mitsuo Konno
IPC分类号： H01L23/66 , H01L23/48
CPC分类号： H01L23/66 , H01L2223/6627 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/05599 , H01L2224/16 , H01L2224/16225 , H01L2224/16235 , H01L2224/48227 , H01L2224/48235 , H01L2224/49171 , H01L2224/73204 , H01L2224/85399 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01079 , H01L2924/01087 , H01L2924/14 , H01L2924/1423 , H01L2924/16152 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/3011 , H01L2924/3025
摘要： A semiconductor module has an MMIC chip flip-chip-mounted on a board. The MMIC chip has a ground line and bumps. The board has through holes and a ground electrode. These ground line, bumps, through holes, and ground electrode form a conductor continuum that defines a quasi-cavity. The module is designed so that the resonance frequency (fr) of the quasi-cavity is higher than the maximum operation frequency (fumax) of the MMIC chip. This prevents signal disturbance due to agreement between the resonance frequency (fr) and an operation frequency (fu) of the MMIC chip. If the MMIC chip is provided with bias circuits having MIM capacitors, the MIM capacitors are formed within the quasi-cavity. The quasi-cavity blocks magnetic fields generated by the MIM capacitors from leaking outside and badly affecting electronic parts arranged around the MMIC chip. The thickness of the MMIC chip is limited within a given range, to prevent coupling between a parasitic transmission line made of the substrate and ground line of the MMIC chip and a main transmission line on the MMIC chip, to thereby secure isolation between input and output signals to and from the MMIC chip.
摘要翻译：半导体模块具有倒装芯片安装在板上的MMIC芯片。 MMIC芯片有地线和颠簸。电路板有通孔和接地电极。这些接地线，凸块，通孔和接地电极形成定义准腔的导体连续体。该模块的设计使得准空腔的谐振频率（fr）高于MMIC芯片的最大工作频率（fumax）。这可以防止由于MMIC芯片的谐振频率（fr）和操作频率（fu）之间的一致性引起的信号干扰。如果MMIC芯片设置有具有MIM电容器的偏置电路，则MIM电容器形成在准腔内。准空腔阻止由MIM电容器产生的磁场泄漏到外部，并且严重影响布置在MMIC芯片周围的电子部件。 MMIC芯片的厚度限制在给定范围内，以防止由衬底制成的寄生传输线和MMIC芯片的接地线与MMIC芯片上的主传输线之间的耦合，从而确保输入和输出之间的隔离信号往返MMIC芯片。

5. 发明授权

US06882204B2 Semiconductor integrated circuit device with differential output driver circuit, and system for semiconductor integrated circuit device 失效
标题翻译：具有差分输出驱动电路的半导体集成电路器件，以及用于半导体集成电路器件的系统
公开(公告)号：US06882204B2
公开(公告)日：2005-04-19
申请号：US10875397
申请日：2004-06-25
申请人： Yasushi Shizuki
发明人： Yasushi Shizuki
IPC分类号： G01R31/28 , H01L21/82 , H01L21/822 , H01L27/04 , H03K19/003 , H03K17/16
CPC分类号： H03K19/00323 , H04L25/0272
摘要： A semiconductor integrated circuit device includes a differential output driver circuit arranged at each I/O portion, and a delay element. The differential output driver circuit receives a pair of differential signals generated by a circuit on the input stage. An output signal from the differential output driver circuit is transmitted through the first and second signal lines. Each of the first and second signal lines includes a global interconnection, bump, and transmission line. The delay element is inserted in at least one of the first and second signal lines. The delay element delays signals passing through the signal lines so as to make the delays of the signals substantially equal to each other, compensating for the signal delay time generated by the line length difference.
摘要翻译：半导体集成电路器件包括布置在每个I / O部分的差分输出驱动器电路和延迟元件。差分输出驱动电路接收由输入级上的电路产生的一对差分信号。来自差分输出驱动电路的输出信号通过第一和第二信号线传输。第一和第二信号线中的每一个包括全局互连，凸起和传输线。延迟元件插入第一和第二信号线中的至少一个。延迟元件延迟通过信号线的信号，使得信号的延迟基本相等，补偿由线长差产生的信号延迟时间。

6. 发明授权

US5898909A Ultra high frequency radio communication apparatus 失效
标题翻译：超高频无线通信装置
公开(公告)号：US5898909A
公开(公告)日：1999-04-27
申请号：US720379
申请日：1996-09-27
申请人： Kunio Yoshihara , Kouhei Morizuka , Mitsuo Konno , Yasuo Ashizawa , Junko Akagi , Yasuhiro Kuriyama , Motoyasu Morinaga , Eiji Takagi , Yasushi Shizuki , Yuji Iseki , Takeshi Hanawa , Takeshi Miyagi
发明人： Kunio Yoshihara , Kouhei Morizuka , Mitsuo Konno , Yasuo Ashizawa , Junko Akagi , Yasuhiro Kuriyama , Motoyasu Morinaga , Eiji Takagi , Yasushi Shizuki , Yuji Iseki , Takeshi Hanawa , Takeshi Miyagi
IPC分类号： H01L25/00 , H01L23/552 , H01L25/065 , H01L25/07 , H01L25/18 , H01P5/08 , H01P7/06 , H01P7/10 , H01Q23/00 , H03D7/00 , H04B1/38 , H04B1/44
CPC分类号： H03D7/00 , H01L23/552 , H01Q23/00 , H04B1/408 , H01L2223/6677 , H01L2224/05554 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/32245 , H01L2224/48137 , H01L2224/48227 , H01L2224/4823 , H01L2224/49175 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2924/00014 , H01L2924/01057 , H01L2924/01079 , H01L2924/10329 , H01L2924/14 , H01L2924/15153 , H01L2924/15159 , H01L2924/15165 , H01L2924/16152 , H01L2924/1616 , H01L2924/16195 , H01L2924/16251 , H01L2924/19041 , H01L2924/19104 , H01L2924/19105 , H01L2924/19107 , H01L2924/3025
摘要： Disclosed is an ultra high frequency radio communication apparatus having: a receiver antenna; a transmitter antenna; an IC chip being electrically connected to the receiver antenna and the transmitter antenna; a substrate on which the receiver antenna, the transmitter antenna and the IC chip are mounted; an input terminal for inputting to the IC chip a base band input signal; an output terminal for outputting a base band output signal from the IC chip; and a control signal terminal for inputting a control signal for controlling the IC chip to the IC chip. The IC chip is placed in a shielding space such that the cut-off frequency of the shielding space is higher than the frequency of a carrier signal for radio communication.
摘要翻译：公开了一种超高频无线通信装置，具有：接收天线; 发射天线; IC芯片电连接到接收机天线和发射机天线; 其上安装有接收天线，发射机天线和IC芯片的基板; 输入端子，用于向IC芯片输入基带输入信号; 输出端子，用于从IC芯片输出基带输出信号; 以及用于输入用于将IC芯片控制到IC芯片的控制信号的控制信号端子。 IC芯片被放置在屏蔽空间中，使得屏蔽空间的截止频率高于用于无线电通信的载波信号的频率。

7. 发明授权

US5764119A Wiring board for high-frequency signals and semiconductor module for high-frequency signals using the wiring board 失效
标题翻译：使用接线板的高频信号接线板和高频信号半导体模块
公开(公告)号：US5764119A
公开(公告)日：1998-06-09
申请号：US725167
申请日：1996-10-03
申请人： Takeshi Miyagi , Yuji Iseki , Yasushi Shizuki , Kunio Yoshihara , Masayuki Saito , Kazuhito Higuchi , Takeshi Hanawa , Eiji Takagi
发明人： Takeshi Miyagi , Yuji Iseki , Yasushi Shizuki , Kunio Yoshihara , Masayuki Saito , Kazuhito Higuchi , Takeshi Hanawa , Eiji Takagi
IPC分类号： H01P3/08 , H05K1/02 , H05K1/14 , H05K3/04 , H05K3/10 , H05K3/46
CPC分类号： H05K3/045 , H01P3/088 , H05K1/0242 , H05K1/144 , H05K2201/09036 , H05K2201/098 , H05K3/107 , H05K3/465
摘要： A wiring board for high-frequency signals, which comprises, a substrate, a dielectric layer formed on the substrate and provided on its surface with a U-shaped groove having an arcuate bottom for forming a wiring therein, and a signal wiring formed in the U-shaped groove, which is featured in that an upper end portion of the signal wiring is protruded out of the surface of the dielectric layer. A distance (H) from a protruded top surface of the signal wiring to a bottom of the U-shaped groove and a width (W) of the U-shaped groove preferably meet a relationship of 2
摘要翻译：一种高频信号用布线基板，其特征在于，包括：基板，形成在所述基板上的电介质层，其表面上形成有用于在其中形成布线的弓形底部的U形槽，以及形成在所述基板上的信号布线 U形槽的特征在于，信号线的上端部突出到电介质层的表面之外。从信号线的突出顶面到U形槽的底部的距离（H）和U形槽的宽度（W）优选满足2 <（W / H）<50的关系，并且从电介质层的表面突出的信号布线的部分的高度优选在10nm至10μm的范围内。

8. 发明授权

US5914536A Semiconductor device and soldering portion inspecting method therefor 失效
标题翻译：半导体器件及其焊接部分检查方法
公开(公告)号：US5914536A
公开(公告)日：1999-06-22
申请号：US678536
申请日：1996-07-05
申请人： Yasushi Shizuki , Yuji Iseki , Naoko Ono , Kunio Yoshihara , Masayuki Saito , Hiroshi Yamada , Kazuki Tateyama
发明人： Yasushi Shizuki , Yuji Iseki , Naoko Ono , Kunio Yoshihara , Masayuki Saito , Hiroshi Yamada , Kazuki Tateyama
IPC分类号： G01R31/04 , H01L21/60 , H01L21/66 , H01L23/485 , H01L23/498 , H05K1/02 , H05K1/11 , H05K1/18 , H05K3/34 , H05K3/36 , H01L23/48
CPC分类号： H01L24/13 , G01R31/048 , H01L23/49816 , H01L24/16 , H01L24/81 , H05K3/3436 , H05K3/3442 , H05K3/3452 , H01L2224/05568 , H01L2224/13099 , H01L2224/131 , H01L2224/16058 , H01L2224/16225 , H01L2224/171 , H01L2224/48091 , H01L2224/48227 , H01L2224/81801 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/0101 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01054 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/10336 , H01L2924/12041 , H01L2924/12042 , H01L2924/15311 , H01L2924/16152 , H01L2924/19105 , H05K1/0203 , H05K1/0269 , H05K2201/0367 , H05K2201/09381 , H05K2201/09427 , H05K2201/0989 , H05K2201/10674 , H05K2201/10727 , H05K2201/10969 , H05K2203/0465 , H05K3/3431 , H05K3/368 , Y02P70/613
摘要： A semiconductor device includes a wiring board having a main surface and a plurality of pad electrodes formed on the main surface, a rectangular semiconductor element having a main surface facing the main surface of the wiring board and mounted on the main surface of the wiring board, a solder resist formed to surround the semiconductor element with a preset distance therefrom on the main surface of the wiring board, a plurality of terminal electrodes formed on the end portion of the main surface of the semiconductor element, and a plurality of solder bumps for electrically connecting the plurality of pad electrodes to the plurality of terminal electrodes with a gap provided between the main surface of the wiring board and the main surface of the semiconductor element, wherein each of the plurality of pad electrodes includes at least a portion which extends from substantially under a corresponding one of the plurality of terminal electrodes of the semiconductor element to the solder resist lying outside the semiconductor element and each of the plurality of solder bumps includes a portion extending over part of a corresponding one of the plurality of pads which lies outside the semiconductor element.
摘要翻译：半导体器件包括具有主表面和形成在主表面上的多个焊盘电极的布线板，具有面向布线板的主表面的主表面并且安装在布线板的主表面上的矩形半导体元件，在该布线基板的主面上形成有围绕半导体元件与预定距离的阻焊剂，形成于该半导体元件的主面的端部的多个端子电极和多个用于电连接的焊料凸块将所述多个焊盘电极连接到所述多个端子电极，所述间隙设置在所述布线板的主表面和所述半导体元件的主表面之间，其中所述多个焊盘电极中的每一个包括至少一部分，在半导体元件的多个端子电极中的对应的一个到焊料re 位于半导体元件外侧的多个焊料块中的每一个包括在位于半导体元件外部的多个焊盘中相应的一个焊盘的一部分上延伸的部分。

9. 发明授权

US5818113A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5818113A
公开(公告)日：1998-10-06
申请号：US713846
申请日：1996-09-12
申请人： Yuji Iseki , Yasushi Shizuki , Hiroshi Yamada , Takashi Togasaki , Kunio Yoshihara
发明人： Yuji Iseki , Yasushi Shizuki , Hiroshi Yamada , Takashi Togasaki , Kunio Yoshihara
IPC分类号： H01L21/56 , H01L21/60 , H01L23/13 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/81 , H01L21/563 , H01L23/13 , H01L24/28 , H01L2224/16225 , H01L2224/16227 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/81801 , H01L2224/83102 , H01L2224/92125 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01039 , H01L2924/01087 , H01L2924/0132 , H01L2924/014 , H01L2924/10329 , H01L2924/1423 , H01L2924/15151 , H01L2924/3011
摘要： A semiconductor device wherein a sealing resin is filled in a space between an interconnecting wiring board and a semiconductor chip after the semiconductor chip is flip chip-mounted on the wiring board in which at least a non-planar region consisting of a through hole, a concave portion or a convex portion, or a region exhibiting poor wettability to the sealing resin is formed on the surface of the wiring board or the semiconductor chip so as to provide a void in the sealed resin filled between the wiring board and the semiconductor chip for the purpose of minimizing any bad influence from the sealing resin on the interconnecting wirings or elements formed on the semiconductor chip.
摘要翻译：一种半导体器件，其中在半导体芯片倒装芯片安装在布线板上之后，在互连线路板和半导体芯片之间的空间中填充密封树脂，其中至少由通孔，在该布线板或半导体芯片的表面上形成凹部或凸部，或者对密封树脂具有差的润湿性的区域，以便在填充在布线板和半导体芯片之间的密封树脂中提供空隙最小化密封树脂对形成在半导体芯片上的互连布线或元件的不良影响的目的。

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