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1. 发明授权

US08065651B2 Implementing hierarchical design-for-test logic for modular circuit design 有权
标题翻译：实现模块化电路设计的分层设计测试逻辑
公开(公告)号：US08065651B2
公开(公告)日：2011-11-22
申请号：US12362284
申请日：2009-01-29
申请人： Rohit Kapur , Anshuman Chandra , Yasunari Kanzawa , Jyotirmoy Saikia
发明人： Rohit Kapur , Anshuman Chandra , Yasunari Kanzawa , Jyotirmoy Saikia
IPC分类号： G06F17/50
CPC分类号： G01R31/318547
摘要： Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.
摘要翻译：本发明的实施例提供了用于在电路上实现分层设计测试（DFT）逻辑的方法和装置。分层DFT逻辑实现可以专用于模块的DFT电路，并且其可以配置用于多个模块的DFT电路以共享顺序输入信号和/或共享顺序输出信号。在操作期间，用于第一模块的DFT电路可以将比特序列从顺序输入信号传播到第二模块的DFT电路，使得比特序列可以包括用于控制DFT电路的一组控制信号值，并且可以包括用于测试模块的压缩测试向量。此外，用于第二模块的DFT电路可以产生顺序响应信号，其结合来自第二模块的压缩响应向量和来自第一模块的DFT电路的顺序响应信号。

2. 发明授权

US07958472B2 Increasing scan compression by using X-chains 有权
标题翻译：通过使用X链增加扫描压缩
公开(公告)号：US07958472B2
公开(公告)日：2011-06-07
申请号：US12242573
申请日：2008-09-30
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
IPC分类号： G06F17/50 , G06F11/22 , G01R31/28
CPC分类号： G01R31/318547
摘要： To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
摘要翻译：为了在IC设计测试期间增加扫描压缩，提供X链方法。在该方法中，识别可能捕获X的扫描单元的子集，然后将其放置在单独的X链上。可以提供卸载选择器和/或卸载压缩机的配置和观察模式。配置和观察模式为非-X链提供了大于针对X链提供的第二压缩的第一压缩。可以基于这种配置和观察模式来修改ATPG。这种X链方法可以完全集成在测试（DFT）流程中，不需要额外的用户输入，对面积和时间的影响可以忽略不计。对于具有高X密度的设计，工业设计的测试生成结果显示出显着增加的压缩率，而不损失覆盖范围。

3. 发明申请

US20100083199A1 Increasing Scan Compression By Using X-Chains 有权
标题翻译：通过使用X链增加扫描压缩
公开(公告)号：US20100083199A1
公开(公告)日：2010-04-01
申请号：US12242573
申请日：2008-09-30
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G01R31/318547
摘要： To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
摘要翻译：为了在IC设计测试期间增加扫描压缩，提供X链方法。在该方法中，识别可能捕获X的扫描单元的子集，然后将其放置在单独的X链上。可以提供卸载选择器和/或卸载压缩机的配置和观察模式。配置和观察模式为非-X链提供了大于针对X链提供的第二压缩的第一压缩。可以基于这种配置和观察模式来修改ATPG。这种X链方法可以完全集成在测试（DFT）流程中，不需要额外的用户输入，对面积和时间的影响可以忽略不计。对于具有高X密度的设计，工业设计的测试生成结果显示出显着增加的压缩率，而不损失覆盖范围。

4. 发明申请

US20100192030A1 METHOD AND APPARATUS FOR IMPLEMENTING A HIERARCHICAL DESIGN-FOR-TEST SOLUTION 有权
标题翻译：实现分层设计的测试方法的方法和装置
公开(公告)号：US20100192030A1
公开(公告)日：2010-07-29
申请号：US12362284
申请日：2009-01-29
申请人： Rohit Kapur , Anshuman Chandra , Yasunari Kanzawa , Jyotirmoy Saikia
发明人： Rohit Kapur , Anshuman Chandra , Yasunari Kanzawa , Jyotirmoy Saikia
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318547
摘要： Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.
摘要翻译：本发明的实施例提供了用于在电路上实现分层设计测试（DFT）逻辑的方法和装置。分层DFT逻辑实现可以专用于模块的DFT电路，并且其可以配置用于多个模块的DFT电路以共享顺序输入信号和/或共享顺序输出信号。在操作期间，用于第一模块的DFT电路可以将比特序列从顺序输入信号传播到第二模块的DFT电路，使得比特序列可以包括用于控制DFT电路的一组控制信号值，并且可以包括测试模块的压缩测试向量。此外，用于第二模块的DFT电路可以产生顺序响应信号，其结合来自第二模块的压缩响应向量和来自第一模块的DFT电路的顺序响应信号。

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