专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07759245B2 Semiconductor device fabricating method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US07759245B2
公开(公告)日：2010-07-20
申请号：US11948932
申请日：2007-11-30
申请人： Yun-Sheng Liu , Wen-Chung Chen
发明人： Yun-Sheng Liu , Wen-Chung Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/28518 , H01L21/823443 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11286
摘要： A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device with a second silicide region and a second silicide block region are formed in the logic device region and the memory device region, respectively. A first insulating layer is formed covering the first and second silicide block regions. A silicide process is performed to form a silicide layer on the first and second silicide regions. An underlying second insulating layer and an insulating barrier layer are formed covering the first insulating layer and the silicide layer.
摘要翻译：描述半导体器件制造方法。半导体器件制造方法包括向基板提供逻辑器件区域和存储器件区域。分别在逻辑器件区域和存储器件区域中分别形成具有第一硅化物区域和第一硅化物块区域的逻辑器件以及具有第二硅化物区域和第二硅化物块区域的存储器件。形成覆盖第一和第二硅化物块区域的第一绝缘层。执行硅化处理以在第一和第二硅化物区域上形成硅化物层。形成覆盖第一绝缘层和硅化物层的下面的第二绝缘层和绝缘阻挡层。

2. 发明申请

US20090212436A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：半导体结构及其形成方法
公开(公告)号：US20090212436A1
公开(公告)日：2009-08-27
申请号：US12038747
申请日：2008-02-27
申请人： Hsin-Chi Sun , Wen-Chung Chen , Chih-Cherng Liao , Sung-Min Wei
发明人： Hsin-Chi Sun , Wen-Chung Chen , Chih-Cherng Liao , Sung-Min Wei
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L24/11 , H01L21/76819 , H01L2224/05567 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05666 , H01L2224/05684 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/19043 , H01L2924/00014
摘要： A semiconductor structure and method for forming the same are provided. The semiconductor structure comprises a semiconductor substrate, a plurality of top metallizations on the semiconductor substrate, a high density plasma layer filling gaps between the top metallizations and having a substantially planar upper surface overlying the top metallizations, and a passivation layer overlying the high density plasma layer. A metal bump can be formed overlying the top metallizations through the passivation layer and HDPCVD layer for subsequent bonding.
摘要翻译：提供一种半导体结构及其形成方法。半导体结构包括半导体衬底，半导体衬底上的多个顶部金属化层，填充顶部金属化之间的间隙的高密度等离子体层，并且具有覆盖顶部金属化的基本平坦的上表面，以及覆盖高密度等离子体的钝化层层。可以通过钝化层和HDPCVD层在顶部金属化层上形成金属凸块用于随后的结合。

3. 发明申请

US20090142918A1 SEMICONDUCTOR DEVICE FABRICATING METHOD 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20090142918A1
公开(公告)日：2009-06-04
申请号：US11948932
申请日：2007-11-30
申请人： Yun-Sheng Liu , Wen-Chung Chen
发明人： Yun-Sheng Liu , Wen-Chung Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/28518 , H01L21/823443 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11286
摘要： A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device with a second silicide region and a second silicide block region are formed in the logic device region and the memory device region, respectively. A first insulating layer is formed covering the first and second silicide block regions. A silicide process is performed to form a silicide layer on the first and second silicide regions. An underlying second insulating layer and an insulating barrier layer are formed covering the first insulating layer and the silicide layer.
摘要翻译：描述半导体器件制造方法。半导体器件制造方法包括向基板提供逻辑器件区域和存储器件区域。分别在逻辑器件区域和存储器件区域中分别形成具有第一硅化物区域和第一硅化物块区域的逻辑器件以及具有第二硅化物区域和第二硅化物块区域的存储器件。形成覆盖第一和第二硅化物块区域的第一绝缘层。执行硅化处理以在第一和第二硅化物区域上形成硅化物层。形成覆盖第一绝缘层和硅化物层的下面的第二绝缘层和绝缘阻挡层。

4. 发明申请

US20090091958A1 DEVICE FOR SIMULATING RECTIFIED CONSTANT IMPEDANCE LOAD AND METHOD THEREOF 有权
标题翻译：用于模拟整流的恒定阻抗负载的装置及其方法
公开(公告)号：US20090091958A1
公开(公告)日：2009-04-09
申请号：US12244346
申请日：2008-10-02
申请人： Hung-Hsiang KAO , Wen-Chung CHEN , Kuo-Cheng LIU , Ming-Ying TSOU
发明人： Hung-Hsiang KAO , Wen-Chung CHEN , Kuo-Cheng LIU , Ming-Ying TSOU
IPC分类号： H02M7/00
CPC分类号： G01R31/42 , G01R31/2848
摘要： The device for simulating a rectified constant impedance load provide by the present invention is to test a power product and comprises an analog-digital converter, a digital signal processor, a digital-analog converter, and an active electrical load module in order to replacing the passive components of a traditional rectified passive load. method for simulating a rectified constant impedance load being applied to test a power product and comprising the steps of: (S1) replacing the plurality of passive components of the rectified constant impedance load with a digital control module and an active electrical load module; (S2) establishing a passive load model function in order to represent the application relationships of the plurality of the passive components; (S3) executing the operation of the passive load model function by the digital control module in order to gain a load current value, and transferring the load current value to an analog control signal via the digital control module; and (S4) controlling the active electrical load module via the analog control signal so as to draw currents from the power product.
摘要翻译：本发明提供的用于模拟整流恒定阻抗负载的装置是测试功率产品，并且包括模拟数字转换器，数字信号处理器，数模转换器和有源电负载模块，以便更换被动元件的传统整流被动负载。用于模拟整流的恒定阻抗负载的方法，用于测试电力产品，并且包括以下步骤：（S1）用数字控制模块和有源电负载模块代替整流的恒定阻抗负载的多个无源部件; （S2）建立无源负载模型功能，以便表示多个无源组件的应用关系; （S3）通过数字控制模块执行无源负载模型功能的操作，以获得负载电流值，并通过数字控制模块将负载电流值传递给模拟控制信号; 和（S4）经由模拟控制信号控制有源电负载模块，以便从电力产品中抽取电流。

5. 发明授权

US07454599B2 Selecting multiple threads for substantially concurrent processing 有权
标题翻译：选择多个线程进行实质并发处理
公开(公告)号：US07454599B2
公开(公告)日：2008-11-18
申请号：US11229808
申请日：2005-09-19
申请人： Yang (Jeff) Jiao , Yiping Chen , Wen-Chung Chen
发明人： Yang (Jeff) Jiao , Yiping Chen , Wen-Chung Chen
IPC分类号： G06F9/312 , G06F9/315
CPC分类号： G06F9/3851 , G06F9/3885
摘要： The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source, then the instructions from the various sources are provided to their corresponding processing units for substantially concurrent processing.
摘要翻译：本公开提供了能够并行执行指令的处理单元和源仲裁器。源仲裁器确定是否从不同的源读取处理单元的指令。如果源仲裁器确定每个处理单元从不同的源读取其相应的指令，则将来自各种源的指令提供给它们对应的处理单元以进行基本并发处理。

6. 发明授权

US07430139B2 Shared memory synchronization systems and methods 有权
标题翻译：共享内存同步系统和方法
公开(公告)号：US07430139B2
公开(公告)日：2008-09-30
申请号：US11451079
申请日：2006-06-12
申请人： Wen-Chung Chen , Jianming Xu , Huizhong Ou , Chienkang Cheng , Shou-Yu Joyce Cheng
发明人： Wen-Chung Chen , Jianming Xu , Huizhong Ou , Chienkang Cheng , Shou-Yu Joyce Cheng
IPC分类号： G11C7/06
CPC分类号： G11C7/1039 , G06F12/084
摘要： The present disclosure provides system and method embodiments for synchronizing access to memory between a plurality of modules in a pipelined system. One system embodiment, among others, includes an upstream module and a downstream module that each share one or more locations in memory. The upstream module is configured to receive a command pair having matched identifiers, one half (wait command) of which enables the upstream module to delay access to the memory to avoid read-after-write (RAW) hazard, the other half (signal command) which is passed to the downstream module. The downstream module passes the identifier from the signal command to the upstream module at a time corresponding to the downstream module reaching an idle state, thus ceasing access to the memory. The upstream module, upon determining that the identifier received over a direct connection from the downstream module is from the command pair, accesses the one or more locations in the memory.
摘要翻译：本公开提供了用于在流水线系统中的多个模块之间同步对存储器的访问的系统和方法实施例。一个系统实施例包括上游模块和下游模块，每个模块在存储器中共享一个或多个位置。上游模块被配置为接收具有匹配标识符的命令对，其一半（等待命令）使得上游模块能够延迟对存储器的访问以避免读写（RAW）危险，另一半（信号命令）传递给下游模块。下游模块在与下游模块相对应的时间到达空闲状态的时候，将信号命令中的标识符从信号命令传递到上游模块，从而停止对存储器的访问。上游模块在确定通过来自下游模块的直接连接接收到的标识符来自命令对时，访问存储器中的一个或多个位置。

7. 发明授权

US07277098B2 Apparatus and method of an improved stencil shadow volume operation 有权
标题翻译：改进的模板阴影体积操作的装置和方法
公开(公告)号：US07277098B2
公开(公告)日：2007-10-02
申请号：US10924068
申请日：2004-08-23
申请人： Jiangming Xu , Wen-Chung Chen , Yuanfeng Wang , Liang Li , John Brothers , Boris Prokopenko
发明人： Jiangming Xu , Wen-Chung Chen , Yuanfeng Wang , Liang Li , John Brothers , Boris Prokopenko
IPC分类号： G06T9/00 , G06T15/50 , G06F12/02
CPC分类号： G06T15/60 , G06T1/60
摘要： The computer graphics system is configured to improve the performance of a stencil shadow volume method for rendering shadows. The apparatus and methods utilize a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels. The compressed stencil buffer is utilized with a compressed stencil buffer cache to perform a stencil shadow volume operation more efficiently than present methods.
摘要翻译：计算机图形系统被配置为提高用于渲染阴影的模板阴影卷方法的性能。该装置和方法利用压缩和未压缩模板缓冲器的组合与压缩和未压缩的深度数据缓冲器协调。未压缩的模板缓冲器能够存储每个像素的模板阴影体积数据，并且压缩模板缓冲器能够存储一组像素的模板阴影体积数据。压缩模板缓冲器与压缩模板缓冲区缓存一起使用，以比当前方法更有效地执行模板阴影卷操作。

8. 发明申请

US20070139423A1 Method and system for multiple GPU support 有权
标题翻译：支持多种GPU的方法和系统
公开(公告)号：US20070139423A1
公开(公告)日：2007-06-21
申请号：US11300980
申请日：2005-12-15
申请人： Dehai Kong , Wen-Chung Chen , Ping Chen , Irene (Chih-Yiieh) Cheng , Tatsang Mak , Xi Liu , Li Zhang , Li Sun , Chenggang Liu
发明人： Dehai Kong , Wen-Chung Chen , Ping Chen , Irene (Chih-Yiieh) Cheng , Tatsang Mak , Xi Liu , Li Zhang , Li Sun , Chenggang Liu
IPC分类号： G06F15/16
CPC分类号： G09G5/363
摘要： Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.
摘要翻译：支持多个图形处理单元（GPU）包括耦合到北桥设备（或根复杂设备）的第一路径和可以包括第一GPU总通信线路的一部分的第一GPU。第二通信路径可以耦合到北桥设备和第二GPU，并且可以包括第二GPU的总通信线路的一部分。第三通信路径可以直接地耦合在第一和第二GPU之间，或者通过一个或多个可以被配置用于单个或多个GPU操作的交换机。第三通信路径可以包括用于第一和第二GPU的剩余通信线路中的一些或全部。作为非限制性示例，第一和第二GPU可以各自利用与北桥设备的8通道PCI快速通信路径和彼此之间的8通道PCI快速通信路径。

9. 发明申请

US20070088877A1 Packet processing systems and methods 有权
标题翻译：数据包处理系统和方法
公开(公告)号：US20070088877A1
公开(公告)日：2007-04-19
申请号：US11549389
申请日：2006-10-13
申请人： Wen-Chung Chen , Li Liang , Shou-Yu Cheng
发明人： Wen-Chung Chen , Li Liang , Shou-Yu Cheng
IPC分类号： G06F13/38
CPC分类号： G06F13/4226
摘要： Packet processing system and method embodiments implemented in a peripheral component interconnect-express (PCIE) compliant system are disclosed. One method embodiment, among others, comprises receiving a packet having at least a first type of data and a second type of data over a PCIE connection, and segregating the entire packet into two contiguous groups, a first group comprising the first type of data and a second group comprising the second type of data.
摘要翻译：公开了在外围组件互连快速（PCIE）兼容系统中实现的分组处理系统和方法实施例。一个方法实施例，其中包括通过PCIE连接接收具有至少第一类型的数据和第二类型的数据的分组，并将整个分组分离成两个连续的组，第一组包括第一类型的数据和第二组包括第二类型的数据。

10. 发明申请

US20070067572A1 Buffering missed requests in processor caches 审中-公开
标题翻译：缓冲处理器缓存中的未请求
公开(公告)号：US20070067572A1
公开(公告)日：2007-03-22
申请号：US11229939
申请日：2005-09-19
申请人： Yang Jiao , Yiping Chen , Wen-Chung Chen
发明人： Yang Jiao , Yiping Chen , Wen-Chung Chen
IPC分类号： G06F12/00
CPC分类号： G06F12/0859
摘要： The present disclosure relates to caches that are capable of improving processor performance. In some embodiments, among others, a cache request is received, and logic within the cache determines whether the received cache request results in a hit on the cache. If the cache request results in a hit on the cache, then that cache request is serviced. Conversely, if the cache request does not result in a hit (e.g., miss, miss-on-miss, hit-on-miss, etc.), then information related to the received cache request is stored in a missed request table. For some embodiments, missed read requests are stored in a missed read request table, while missed write requests are stored in a missed write request table.
摘要翻译：本公开涉及能够提高处理器性能的高速缓存。在一些实施例中，其中包括缓存请求被接收，高速缓存内的逻辑确定所接收的高速缓存请求是否导致高速缓存的命中。如果缓存请求导致高速缓存中的命中，则该缓存请求被服务。相反，如果缓存请求不导致命中（例如，未命中，未命中，命中等等），则与所接收的高速缓存请求相关的信息被存储在错过的请求表中。对于一些实施例，错过的读取请求被存储在错过的读取请求表中，而错过的写入请求被存储在错过的写入请求表中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式