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1. 发明申请

US20130009741A1 INTEGRATED CIRCUIT TRANSFORMER 有权
标题翻译：集成电路变压器
公开(公告)号：US20130009741A1
公开(公告)日：2013-01-10
申请号：US13474677
申请日：2012-05-17
申请人： Cheng-Chou HUNG , Cheng-Jyi CHANG , Tung-Hsing LEE , Wei-Che HUANG
发明人： Cheng-Chou HUNG , Cheng-Jyi CHANG , Tung-Hsing LEE , Wei-Che HUANG
IPC分类号： H01F27/28
CPC分类号： H01F19/04 , H01F27/2804 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern.
摘要翻译：本发明提供一种设置在基板上的集成电路变压器。集成电路变压器包括设置在基板上的第一卷绕金属图案，包括内环段和外环段。第二卷绕金属图案设置在衬底上，横向在内环段和外环段之间。电介质层设置在第一卷绕金属图案和第二卷绕金属图案上。通过介电层形成第一通孔，电连接到第一和第二卷绕金属图案之一。第一再分配图案设置在电介质层上，电连接并沿着第一通孔延伸，其中第一再分配图案覆盖第一卷绕金属图案的至少一部分和第二卷绕金属图案的至少一部分。

2. 发明授权

US06242334B1 Multi-step spacer formation of semiconductor devices 有权
标题翻译：半导体器件的多步间隔物形成
公开(公告)号：US06242334B1
公开(公告)日：2001-06-05
申请号：US09274597
申请日：1999-03-23
申请人： Michael Wei-Che Huang , Jui-Tsen Huang , Ling Lu , Tri-Rung Yew
发明人： Michael Wei-Che Huang , Jui-Tsen Huang , Ling Lu , Tri-Rung Yew
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/31116 , H01L29/4983 , H01L29/665 , H01L29/6656
摘要： A method for forming a semiconductor with overetched spacer is disclosed. The method includes firstly providing a semiconductor substrate with a gate oxide layer formed thereon, and forming a polysilicon layer on the gate oxide layer. Next, a photoresist layer is formed on the polysilicon layer to define a gate area, followed by anisotropically etching the polysilicon layer and the gate oxide layer. A first dielectric layer is conformably formed, and a second dielectric layer is then formed thereon. After anisotropically etching the second dielectric layer to form a first sidewall spacer on the sidewall of the first dielectric layer, a third dielectric layer is further formed over the exposed first dielectric layer and the first sidewall spacer. Finally, the third dielectric layer and the first sidewall spacer are anisotropically etched so that a second sidewall spacer is formed on the sidewall of the first sidewall spacer, wherein top surface of the first and the second sidewall spacer is below top surface of the first dielectric layer around the gate area.
摘要翻译：公开了一种用椭圆形间隔物形成半导体的方法。该方法包括首先提供其上形成有栅极氧化物层的半导体衬底，并在栅极氧化物层上形成多晶硅层。接下来，在多晶硅层上形成光致抗蚀剂层以限定栅极区域，然后各向异性蚀刻多晶硅层和栅极氧化物层。顺应地形成第一电介质层，然后在其上形成第二电介质层。在各向异性蚀刻第二电介质层以在第一介电层的侧壁上形成第一侧壁间隔物之后，在暴露的第一介电层和第一侧壁间隔物上进一步形成第三电介质层。最后，第三介电层和第一侧壁间隔物被各向异性地蚀刻，使得第二侧壁间隔物形成在第一侧壁间隔物的侧壁上，其中第一和第二侧壁间隔物的顶表面在第一电介质的顶表面下方层围绕门区。

3. 发明授权

US08816810B2 Integrated circuit transformer 有权
标题翻译：集成电路变压器
公开(公告)号：US08816810B2
公开(公告)日：2014-08-26
申请号：US13474677
申请日：2012-05-17
申请人： Cheng-Chou Hung , Cheng-Jyi Chang , Tung-Hsing Lee , Wei-Che Huang
发明人： Cheng-Chou Hung , Cheng-Jyi Chang , Tung-Hsing Lee , Wei-Che Huang
IPC分类号： H01F5/00
CPC分类号： H01F19/04 , H01F27/2804 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： The invention provides an integrated circuit transformer disposed on a substrate. The integrated circuit transformer includes a first coiled metal pattern disposed on the substrate, comprising an inner loop segment and an outer loop segment. A second coiled metal pattern is disposed on the substrate, laterally between the inner loop segment and the outer loop segment. A dielectric layer is disposed on the first coiled metal pattern and the second coiled metal pattern. A first via is formed through the dielectric layer, electrically connecting to one of the first and second coiled metal patterns. A first redistribution pattern is disposed on the dielectric layer, electrically connecting to and extending along the first via, wherein the first redistribution pattern covers at least a portion of the first coiled metal pattern and at least a portion of the second coiled metal pattern.
摘要翻译：本发明提供一种设置在基板上的集成电路变压器。集成电路变压器包括设置在基板上的第一卷绕金属图案，包括内环段和外环段。第二卷绕金属图案设置在衬底上，横向在内环段和外环段之间。电介质层设置在第一卷绕金属图案和第二卷绕金属图案上。通过介电层形成第一通孔，电连接到第一和第二卷绕金属图案之一。第一再分配图案设置在电介质层上，电连接并沿着第一通孔延伸，其中第一再分配图案覆盖第一卷绕金属图案的至少一部分和第二卷绕金属图案的至少一部分。

4. 发明申请

US20060279563A1 METHOD FOR CALIBRATING FLAT PANEL DISPLAY 审中-公开
标题翻译：校准平板显示器的方法
公开(公告)号：US20060279563A1
公开(公告)日：2006-12-14
申请号：US11162114
申请日：2005-08-29
申请人： Yu-Chuan Shen , Wei-Che Huang
发明人： Yu-Chuan Shen , Wei-Che Huang
IPC分类号： G09G5/00
CPC分类号： G09G3/2092 , G09G2320/0693
摘要： A method for calibrating a flat panel display comprising the following steps is provided. First, initialize a flat panel display and an optical meter. Provide a predetermined period of delay. Use the flat panel display to display a test pattern. Provide another predetermined period of delay. Use the optical meter to get measured data from the test pattern repeatedly until enough data for analysis is gathered. Repeat the step of displaying the test patterns until all test patterns have been displayed. Finally, analyze all the measured data to calculate the correct parameters for the control circuit of the flat panel display and set the parameters of the control circuit to the correct values.
摘要翻译：提供了一种用于校准平板显示器的方法，包括以下步骤。首先，初始化平板显示器和光学仪表。提供预定的延迟时间。使用平板显示屏显示测试图案。提供另一个预定的延迟时间。使用光度计从测试图中重复得到测量数据，直到收集足够的数据用于分析。重复显示测试图案的步骤，直到显示所有测试图案。最后，分析所有测量数据，以计算平板显示器控制电路的正确参数，并将控制电路的参数设置为正确的值。

5. 发明授权

US06221772B1 Method of cleaning the polymer from within holes on a semiconductor wafer 有权
标题翻译：从半导体晶片上的孔内清洗聚合物的方法
公开(公告)号：US06221772B1
公开(公告)日：2001-04-24
申请号：US09352747
申请日：1999-07-14
申请人： Chan-Lon Yang , Tong-Yu Chen , Wei-Che Huang
发明人： Chan-Lon Yang , Tong-Yu Chen , Wei-Che Huang
IPC分类号： H01L21302
CPC分类号： H01L21/02063 , C11D7/02 , C11D11/0047 , G03F7/427 , H01L21/31138 , H01L21/76814
摘要： The present invention provides a method of in-situ cleaning polymers from holes on a semiconductor wafer and in-situ removing the silicon nitride layer. The semiconductor wafer comprising a substrate, a silicon nitride (Si3N4) layer on the substrate, a silicon oxide (SiO2) layer on the silicon nitride layer, and a photo-resist layer on the silicon oxide layer. The silicon oxide layer and the photo-resist layer have a hole extending down to the silicon nitride layer. The hole contains polymer left after etching of the silicon oxide layer. The method comprises performing a in-situ plasma ashing process by injecting oxygen (O2) and argon (Ar) to completely remove the photo-resist layer and the polymer remaining within the hole. Subsequently, the silicon nitride layer was removed in the same chamber. The flow rate of O2 is maintained between 50˜2000 sccm (standard cubic centimeter per minute) and the flow rate of Ar is maintained between 50˜500 sccm.
摘要翻译：本发明提供了一种从半导体晶片上的孔中原位清洗聚合物并原位去除氮化硅层的方法。包括衬底，衬底上的氮化硅（Si 3 N 4）层，氮化硅层上的氧化硅（SiO 2）层和氧化硅层上的光致抗蚀剂层的半导体晶片。氧化硅层和光致抗蚀剂层具有向下延伸到氮化硅层的孔。该孔含有在氧化硅层蚀刻后残留的聚合物。该方法包括通过注入氧（O 2）和氩（Ar）进行原位等离子体灰化处理，以完全除去光刻胶层和留在孔内的聚合物。随后，在相同的室中除去氮化硅层。 O2的流量保持在50〜2000sccm（标准立方厘米每分钟）之间，Ar的流量保持在50〜500sccm之间。

6. 发明授权

US6147007A Method for forming a contact hole on a semiconductor wafer 有权
标题翻译：在半导体晶片上形成接触孔的方法
公开(公告)号：US6147007A
公开(公告)日：2000-11-14
申请号：US330597
申请日：1999-06-11
申请人： Chan-Lon Yang , Wei-Che Huang , Tong-Yu Chen
发明人： Chan-Lon Yang , Wei-Che Huang , Tong-Yu Chen
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76802 , H01L21/76814
摘要： The present invention relates to a method of forming a contact hole on the semiconductor wafer. The semiconductor wafer comprises, in ascending order, a substrate, a silicon nitride layer, a silicon oxide layer, and a photo-resist layer. There is a hole in the photo-resist layer. The method comprises: (1) performing a first anisotropic etching process in a downward direction to remove the silicon oxide layer under the hole down to the surface of the silicon nitride layer to form a recess; (2) performing an in-situ plasma cleaning process to entirely remove the polymer material remaining at the bottom of the recess; (3) performing an in-situ second anisotropic etching process in a downward direction to remove the silicon nitride layer from the bottom of the recess down to the surface of the substrate to form the contact hole; (4) performing another in-situ cleaning process to entirely remove the polymer material remaining at the bottom of the contact hole.
摘要翻译：本发明涉及在半导体晶片上形成接触孔的方法。半导体晶片按照升序包括衬底，氮化硅层，氧化硅层和光致抗蚀剂层。光致抗蚀剂层中有一个孔。该方法包括：（1）沿向下的方向进行第一各向异性蚀刻处理，以将氧化硅层下面的氮化硅层的表面去除，形成凹部; （2）进行原位等离子体清洗工艺以完全除去残留在凹部底部的聚合物材料; （3）在向下的方向上进行原位第二各向异性蚀刻工艺，以将氮化硅层从凹槽的底部向下移动到衬底的表面，以形成接触孔; （4）进行另一原位清洗处理以完全除去留在接触孔底部的聚合物材料。

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