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1. 发明授权

US06396764B1 Segmented memory architecture and systems and methods using the same 有权
标题翻译：分段内存架构和使用相同的系统和方法
公开(公告)号：US06396764B1
公开(公告)日：2002-05-28
申请号：US09715669
申请日：2000-11-16
申请人： Wayland Bart Holland
发明人： Wayland Bart Holland
IPC分类号： G11C800
CPC分类号： G11C7/1042 , G11C7/1006 , G11C8/16
摘要： A memory 200 includes a first memory segment 302 comprising an array of rows and columns of memory cells, a selected column of cells in the first segment 302 accessed through a dedicated sense amplifier 304 associated with the first segment. A second memory segment 302 comprises an array of rows and columns of memory cells, a selected column of cells in the second memory segment 302 accessed through a dedicated sense amplifier 304 associated with the second segment. A Read Input/Output line 306a is coupled to the sense amplifier accessing the selected column of the first segment 302 for reading data from the first segment during a selected access cycle. A Write Input/Output line 306b is coupled to the sense amplifier 304 accessing the selected column of the second segment 302 for simultaneously writing data to the second memory segment 302 during the selected access cycle.
摘要翻译：存储器200包括包括存储器单元的行和列的阵列的第一存储器段302，通过与第一段相关联的专用读出放大器304访问第一段302中的选定列的单元。第二存储器段302包括存储器单元的行和列的阵列，通过与第二段相关联的专用读出放大器304访问第二存储器段302中的选定列的单元。读入输入/输出线306a耦合到访问第一段302的选定列的读出放大器，以在选定的访问周期期间从第一段读取数据。写入输入/输出线306b耦合到读出放大器304，访问第二段302的选定列，以在所选择的访问周期期间同时将数据写入第二存储器段302。

2. 发明授权

US5940329A Memory architecture and systems and methods using the same 失效
公开(公告)号：US5940329A
公开(公告)日：1999-08-17
申请号：US992416
申请日：1997-12-17
申请人： Stephen Earl Seitsinger , Wayland Bart Holland
发明人： Stephen Earl Seitsinger , Wayland Bart Holland
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/10
摘要： A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.

3. 发明授权

US5963497A Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same 失效
标题翻译：具有同时访问和刷新操作的动态随机存取存储器系统及其使用方法
公开(公告)号：US5963497A
公开(公告)日：1999-10-05
申请号：US080813
申请日：1998-05-18
申请人： Wayland Bart Holland
发明人： Wayland Bart Holland
IPC分类号： G11C11/405 , G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A memory 200 including an array 201 of rows and columns of 2-transistor, 1-capacitor memory cells 301 of the cells of each row coupled to first and second wordlines 303a, 303b and the cells of each column coupled to a pair of bitlines 302a, 302b. Refresh circuitry 208 activates the first wordline 303a plus selected said row and refreshes the cells 301 of that row through a first one of the bitlines 302a of each of the columns. Data access circuitry 202, 204 substantially simultaneously activates the second said wordline 303b of a second selected row and accesses selected cells of the second row through a second one of the bitlines 302b in the corresponding columns.
摘要翻译：存储器200，其包括耦合到第一和第二字线303a，303b的每行的单元的单元的2-晶体管，1-电容器存储单元301的行和列的阵列201以及耦合到一对位线302a的每列的单元，302b。刷新电路208激活第一字线303a加上所选择的行，并且通过列中的每一列的位线302a中的第一位刷新该行的单元301。数据访问电路202,204基本上同时激活第二选定行的第二所述字线303b，并且通过相应列中的位线302b中的第二行访问第二行的选定单元。

4. 发明授权

US06418063B1 Memory architecture and systems and methods using the same 有权
标题翻译：内存架构和使用相同的系统和方法
公开(公告)号：US06418063B1
公开(公告)日：2002-07-09
申请号：US09543241
申请日：1999-05-14
申请人： Stephen Earl Seitsinger , Wayland Bart Holland
发明人： Stephen Earl Seitsinger , Wayland Bart Holland
IPC分类号： G11C1604
CPC分类号： G11C7/1006 , G11C7/10
摘要： A memory architecture 400 includes an array of memory cells partitioned into a plurality of subarrays 401. Each subarray 401 includes a plurality of memory cells organized in rows and columns, each row associated with a conductive wordline 407 and each column associated with a pair of conductive half-bitlines 403. The first sense amplifier 402 is selectively coupled to selected pair of half-bitlines 403. A second sense amplifier 402 is selectively coupled to the selected pair of half-bitlines 403. A first local I/O line 404 is coupled to first sense amplifier 402 and a second local I/O line 404 is coupled to the second sense amplifier 402. First and second sets of global I/O lines 405 are selectively coupled to the first and second I/O lines 404.
摘要翻译：存储器架构400包括分成多个子阵列401的存储器单元的阵列。每个子阵列401包括以行和列组织的多个存储器单元，每行与导电字线407相关联，每列与一对导电第一读出放大器402选择性地耦合到所选择的一对半位线403.第二读出放大器402选择性地耦合到所选择的一对半位线403。第一本地I / O线404被耦合第一感测放大器402和第二本地I / O线404耦合到第二读出放大器402.第一和第二组全局I / O线405选择性地耦合到第一和第二I / O线404。

5. 发明授权

US06282606B1 Dynamic random access memories with hidden refresh and utilizing one-transistor, one-capacitor cells, systems and methods 有权
标题翻译：具有隐藏刷新和利用单晶体管，单电容器单元，系统和方法的动态随机存取存储器
公开(公告)号：US06282606B1
公开(公告)日：2001-08-28
申请号：US09285869
申请日：1999-04-02
申请人： Wayland Bart Holland
发明人： Wayland Bart Holland
IPC分类号： G06F1200
CPC分类号： G11C11/406
摘要： Memory 200 having an array of rows and columns of memory cells, each column associated with a pair of complementary bitlines 302a, 302b. An access sense amplifier 203 coupled to each pair of complementary bitlines 302a, 302b for sensing and latching data from cells along a selected row during a first portion of a random access cycle. Refresh sense amplifier 204 is coupled to each pair of complementary bitlines for 302a, 302b for refreshing data from cells along a selected row during a second portion of the random access cycle.
摘要翻译：存储器200具有存储器单元的行和列的阵列，每列与一对互补位线302a，302b相关联。耦合到每对互补位线302a，302b的访问读出放大器203，用于在随机访问周期的第一部分期间，沿着所选择的行从单元读取和锁存数据。刷新读出放大器204耦合到每对互补位线302a，302b，用于在随机存取周期的第二部分期间沿着所选行的单元从单元刷新数据。

6. 发明授权

US5995409A Electrically-programmable read-only memory fabricated using a dynamic random access memory fabrication process and methods for programming same 失效
标题翻译：使用动态随机存取存储器制造工艺制造的电可编程只读存储器和用于编程的方法
公开(公告)号：US5995409A
公开(公告)日：1999-11-30
申请号：US45259
申请日：1998-03-20
申请人： Wayland Bart Holland
发明人： Wayland Bart Holland
IPC分类号： G11C17/06 , G11C14/00 , G11C17/14 , H01L21/8242 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/24
CPC分类号： G11C17/14
摘要： A method of permanently programming selected cells of dynamic random access memory cell array. First selected cell is programmed to a Logic 1 by grounding a first capacitor plate of the first cell, and applying a programming voltage to a second capacitor plate common to the cells of the array. A dielectric disposed between the first capacitor plate and the second capacitor plate breaks down, thereby shorting the first and second capacitor plates. A second selected cell is programmed to store a Logic 1 by allowing a first capacitor of the second cell to float during a period when the programming voltage is applied to the second capacitor plate.
摘要翻译：一种永久编程动态随机存取存储单元阵列的选定单元的方法。通过将第一单元的第一电容器板接地并将编程电压施加到阵列的单元共用的第二电容器板，将第一选定单元编程到逻辑1。设置在第一电容器板和第二电容器板之间的电介质分解，从而使第一和第二电容器板短路。第二选择的单元被编程为通过允许第二单元的第一电容器在编程电压施加到第二电容器板的时段期间浮动来存储逻辑1。

7. 发明授权

US06256221B1 Arrays of two-transistor, one-capacitor dynamic random access memory cells with interdigitated bitlines 有权
标题翻译：具有交叉位线的双晶体管，单电容动态随机存取存储器单元阵列
公开(公告)号：US06256221B1
公开(公告)日：2001-07-03
申请号：US09507106
申请日：2000-02-17
申请人： Wayland Bart Holland , Craig Waller , G. R. Mohan Rao
发明人： Wayland Bart Holland , Craig Waller , G. R. Mohan Rao
IPC分类号： G11C1124
CPC分类号： G11C7/18 , G11C8/12 , G11C8/16 , G11C11/405 , G11C11/406 , G11C11/4097
摘要： A memory 1300 including an array of rows and columns of memory cells 501 is disclosed. For each column, first and second interdigitated bitlines 1301, 1303 are coupled to the cells of the column. The first bitlines 1301 has an end coupled to a sense amplifier 1302 at a first boundary of the array and a second bitline 1303 has an end coupled to a second sense amplifier at a second boundary of the array, the first and second boundaries being spaced apart by the array. Control circuitry 508 precharges the first bitlines 1301 of the columns of the array substantially simultaneous to an access to the array through the second bitlines 1303 of selected columns of the array.
摘要翻译：公开了包括存储单元501的行和列的阵列的存储器1300。对于每列，第一和第二叉指位1301,1303耦合到列的单元。第一位线1301具有在阵列的第一边界处耦合到读出放大器1302的一端，并且第二位线1303具有在阵列的第二边界处耦合到第二读出放大器的一端，第一和第二边界被间隔开由阵列。控制电路508通过阵列的所选列的第二位线1303预先对阵列的第一位线1301进行预充电，基本上同时进入对阵列的访问。

8. 发明授权

US06222786B1 Dynamic random access memory with write-without-restore and systems and methods using the same 有权
标题翻译：动态随机存取存储器，具有写 - 无还原功能，系统和方法使用相同
公开(公告)号：US06222786B1
公开(公告)日：2001-04-24
申请号：US09432307
申请日：1999-11-02
申请人： Wayland Bart Holland , Craig Waller , Jason Stevens , Gary Johnson
发明人： Wayland Bart Holland , Craig Waller , Jason Stevens , Gary Johnson
IPC分类号： G11C700
CPC分类号： G06F12/0893 , G06F2212/3042 , G11C8/16 , G11C11/403 , G11C11/4076 , G11C11/4093
摘要： A dynamic random access memory 400 includes an array 401 of physical rows and columns of memory cells, the cells of each row coupled to first and second wordlines 603 and first and second bitlines 602. A direct input/output data path 402 having a width equal to a width of the rows supports simultaneous writing to each of the cells along a selected row using the first wordlines and first bitlines during a single access cycle without restore.
摘要翻译：动态随机存取存储器400包括存储器单元的物理行和列的阵列401，每行的单元耦合到第一和第二字线603以及第一和第二位线602.具有宽度相等的直接输入/输出数据路径402 对于行的宽度，支持在单个访问周期期间使用第一字线和第一位线沿着所选行同时写入每个单元，而不进行恢复。

9. 发明授权

US06222216B1 Non-volatile and memory fabricated using a dynamic memory process and method therefor 失效
标题翻译：使用动态存储器处理及其方法制造的非易失性和存储器
公开(公告)号：US06222216B1
公开(公告)日：2001-04-24
申请号：US08955045
申请日：1997-10-21
申请人： G. R. Mohan Rao , Wayland Bart Holland
发明人： G. R. Mohan Rao , Wayland Bart Holland
IPC分类号： H01L2976
CPC分类号： G06F12/06 , G11C7/065 , H01L27/105 , H01L27/1052 , Y02D10/13
摘要： A data processing system having a DRAM and a non-volatile memory, such as a ROM or a programmable ROM (PROM), is implemented on a single integrated circuit using DRAM data processing techniques. The DRAM is manufactured in accordance with known processing techniques. The non-volatile memory is manufactured using the same DRAM manufacturing techniques, with the addition of a processing step in which a first terminal of a stacked capacitor manufactured in accordance with the DRAM process, is coupled to a known-reference voltage. This stacked capacitor structure may be coupled to a known conductor through the formation of a via and the subsequent coupling of a conductor to the stacked capacitor structure through the via. Alternatively, the stacked capacitor structure may be coupled to the known reference voltage through an internal connection to that reference voltage. By using such methodologies, a data processing system is implemented having a DRAM and a non-volatile memory on a single integrated circuit using a same process methodology.
摘要翻译：具有DRAM和诸如ROM或可编程ROM（PROM）的非易失性存储器的数据处理系统使用DRAM数据处理技术在单个集成电路上实现。 DRAM根据已知的处理技术制造。使用相同的DRAM制造技术制造非易失性存储器，通过添加根据DRAM工艺制造的堆叠电容器的第一端子耦合到已知参考电压的处理步骤。该叠层电容器结构可以通过形成通孔和随后通过通孔将导体耦合到叠层电容器结构而与已知导体耦合。或者，堆叠的电容器结构可以通过与该参考电压的内部连接而耦合到已知的参考电压。通过使用这样的方法，使用相同的处理方法在单个集成电路上实现具有DRAM和非易失性存储器的数据处理系统。

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